singt.tan.qmsg

用VHDL语言描述的用锁存器

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll_w:inst1\|altpll:altpll_component\|_clk0 memory rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|ram_block1a1~porta_address_reg9 memory rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\] 4.924 ns " "Info: Slack time is 4.924 ns for clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" between source memory \"rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|ram_block1a1~porta_address_reg9\" and destination memory \"rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "197.01 MHz 5.076 ns " "Info: Fmax is 197.01 MHz (period= 5.076 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.243 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 9.243 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.946 ns " "Info: + Latch edge is 7.946 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll_w:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll_w:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Largest " "Info: + Largest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_w:inst1\|altpll:altpll_component\|_clk0 destination 2.445 ns + Shortest memory " "Info: + Shortest clock path from clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" to destination memory is 2.445 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_w:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 50; CLK Node = 'pll_w:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll_w:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/61/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.708 ns) 2.445 ns rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\] 2 MEM M4K_X19_Y11 1 " "Info: 2: + IC(1.737 ns) + CELL(0.708 ns) = 2.445 ns; Loc. = M4K_X19_Y11; Fanout = 1; MEM Node = 'rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns ( 28.96 % ) " "Info: Total cell delay = 0.708 ns ( 28.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 71.04 % ) " "Info: Total interconnect delay = 1.737 ns ( 71.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 1.737ns } { 0.000ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_w:inst1\|altpll:altpll_component\|_clk0 source 2.459 ns - Longest memory " "Info: - Longest clock path from clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" to source memory is 2.459 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_w:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 50; CLK Node = 'pll_w:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll_w:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/61/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.722 ns) 2.459 ns rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|ram_block1a1~porta_address_reg9 2 MEM M4K_X19_Y11 2 " "Info: 2: + IC(1.737 ns) + CELL(0.722 ns) = 2.459 ns; Loc. = M4K_X19_Y11; Fanout = 2; MEM Node = 'rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 63 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns ( 29.36 % ) " "Info: Total cell delay = 0.722 ns ( 29.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 70.64 % ) " "Info: Total interconnect delay = 1.737 ns ( 70.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.737ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 1.737ns } { 0.000ns 0.708ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.737ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 63 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 1.737ns } { 0.000ns 0.708ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.737ns } { 0.000ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|ram_block1a1~porta_address_reg9 1 MEM M4K_X19_Y11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y11; Fanout = 2; MEM Node = 'rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|ram_block1a1~porta_address_reg9'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 63 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\] 2 MEM M4K_X19_Y11 1 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X19_Y11; Fanout = 1; MEM Node = 'rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 1.737ns } { 0.000ns 0.708ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.459 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 } { 0.000ns 1.737ns } { 0.000ns 0.722ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "in_clk " "Info: No valid register-to-register data paths exist for clock \"in_clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll_w:inst1\|altpll:altpll_component\|_clk0 register add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\] register add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\] 1.323 ns " "Info: Minimum slack time is 1.323 ns for clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" between source register \"add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\]\" and destination register \"add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.114 ns + Shortest register register " "Info: + Shortest register to register delay is 1.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\] 1 REG LC_X18_Y11_N8 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y11_N8; Fanout = 6; REG Node = 'add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "db/cntr_jeh.tdf" "" { Text "E:/singt/db/cntr_jeh.tdf" 114 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.507 ns) + CELL(0.607 ns) 1.114 ns add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\] 2 REG LC_X18_Y11_N8 6 " "Info: 2: + IC(0.507 ns) + CELL(0.607 ns) = 1.114 ns; Loc. = LC_X18_Y11_N8; Fanout = 6; REG Node = 'add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "db/cntr_jeh.tdf" "" { Text "E:/singt/db/cntr_jeh.tdf" 114 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 54.49 % ) " "Info: Total cell delay = 0.607 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.507 ns ( 45.51 % ) " "Info: Total interconnect delay = 0.507 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.114 ns" { add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 0.507ns } { 0.000ns 0.607ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.054 ns " "Info: + Latch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll_w:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.054 ns  50 " "Info: Clock period of Destination clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.054 ns " "Info: - Launch edge is -2.054 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll_w:inst1\|altpll:altpll_component\|_clk0 10.000 ns -2.054 ns  50 " "Info: Clock period of Source clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" is 10.000 ns with  offset of -2.054 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_w:inst1\|altpll:altpll_component\|_clk0 destination 2.448 ns + Longest register " "Info: + Longest clock path from clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_w:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 50; CLK Node = 'pll_w:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll_w:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/61/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.711 ns) 2.448 ns add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\] 2 REG LC_X18_Y11_N8 6 " "Info: 2: + IC(1.737 ns) + CELL(0.711 ns) = 2.448 ns; Loc. = LC_X18_Y11_N8; Fanout = 6; REG Node = 'add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "db/cntr_jeh.tdf" "" { Text "E:/singt/db/cntr_jeh.tdf" 114 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.04 % ) " "Info: Total cell delay = 0.711 ns ( 29.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 70.96 % ) " "Info: Total interconnect delay = 1.737 ns ( 70.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_w:inst1\|altpll:altpll_component\|_clk0 source 2.448 ns - Shortest register " "Info: - Shortest clock path from clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_w:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 50; CLK Node = 'pll_w:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll_w:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/61/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.711 ns) 2.448 ns add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\] 2 REG LC_X18_Y11_N8 6 " "Info: 2: + IC(1.737 ns) + CELL(0.711 ns) = 2.448 ns; Loc. = LC_X18_Y11_N8; Fanout = 6; REG Node = 'add_count:inst2\|lpm_counter:lpm_counter_component\|cntr_jeh:auto_generated\|safe_q\[8\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "db/cntr_jeh.tdf" "" { Text "E:/singt/db/cntr_jeh.tdf" 114 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 29.04 % ) " "Info: Total cell delay = 0.711 ns ( 29.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 70.96 % ) " "Info: Total interconnect delay = 1.737 ns ( 70.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_jeh.tdf" "" { Text "E:/singt/db/cntr_jeh.tdf" 114 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "db/cntr_jeh.tdf" "" { Text "E:/singt/db/cntr_jeh.tdf" 114 8 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.114 ns" { add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.114 ns" { add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 0.507ns } { 0.000ns 0.607ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.448 ns" { pll_w:inst1|altpll:altpll_component|_clk0 add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] } { 0.000ns 1.737ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}