singt.sim.rpt

用VHDL语言描述的用锁存器

The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                       ; Output Port Name                                                                                          ; Output Port Type ;
+-------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------+
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a9 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[9]                 ; portadataout0    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a9 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[8]                 ; portadataout1    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a9 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[7]                 ; portadataout2    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a9 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[6]                 ; portadataout3    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a5 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[5]                 ; portadataout0    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a5 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[4]                 ; portadataout1    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a5 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[3]                 ; portadataout2    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a5 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[2]                 ; portadataout3    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[1]                 ; portadataout0    ;
; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1 ; |singt|rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0]                 ; portadataout1    ;
; |singt|pll_w:inst1|altpll:altpll_component|pll                                                  ; |singt|pll_w:inst1|altpll:altpll_component|_clk0                                                          ; clk0             ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella0 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[0]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella0 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella0~COUT      ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella0 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella0~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella1 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[1]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella1 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella1~COUT      ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella1 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella1~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella2 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[2]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella2 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella2~COUT      ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella2 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella2~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella3 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[3]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella3 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella3~COUT      ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella3 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella3~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella4 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[4]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella4 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella4~COUT      ; cout             ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella5 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[5]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella5 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella5~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella6 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[6]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella6 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella6~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella7 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[7]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella7 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella7~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella8 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8]                ; regout           ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella8 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella8~COUTCOUT1 ; cout1            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella9 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[9]                ; regout           ;
; |singt|sin_out[9]                                                                               ; |singt|sin_out[9]                                                                                         ; padio            ;
; |singt|sin_out[8]                                                                               ; |singt|sin_out[8]                                                                                         ; padio            ;
; |singt|sin_out[7]                                                                               ; |singt|sin_out[7]                                                                                         ; padio            ;
; |singt|sin_out[6]                                                                               ; |singt|sin_out[6]                                                                                         ; padio            ;
; |singt|sin_out[5]                                                                               ; |singt|sin_out[5]                                                                                         ; padio            ;
; |singt|sin_out[4]                                                                               ; |singt|sin_out[4]                                                                                         ; padio            ;
; |singt|sin_out[3]                                                                               ; |singt|sin_out[3]                                                                                         ; padio            ;
; |singt|sin_out[2]                                                                               ; |singt|sin_out[2]                                                                                         ; padio            ;
; |singt|sin_out[1]                                                                               ; |singt|sin_out[1]                                                                                         ; padio            ;
; |singt|sin_out[0]                                                                               ; |singt|sin_out[0]                                                                                         ; padio            ;
; |singt|in_clk                                                                                   ; |singt|in_clk                                                                                             ; combout          ;
+-------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                  ;
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                       ; Output Port Name                                                                                     ; Output Port Type ;
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella5 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella5~COUT ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella6 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella6~COUT ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella7 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella7~COUT ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella8 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella8~COUT ; cout0            ;
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                                                                  ;
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                       ; Output Port Name                                                                                     ; Output Port Type ;
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella5 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella5~COUT ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella6 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella6~COUT ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella7 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella7~COUT ; cout0            ;
; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella8 ; |singt|add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella8~COUT ; cout0            ;
+-------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 14 09:59:27 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off singt -c singt
Info: Using vector source file "E:/singt/singt.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: PLL "|singt|pll_w:inst1|altpll:altpll_component|pll" was locked to input clock at time 113.32 ns
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      91.84 %
Info: Number of transitions in simulation is 1509943
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 94 megabytes of memory during processing
    Info: Processing ended: Tue Apr 14 10:00:56 2009
    Info: Elapsed time: 00:01:29