singt.fit.rpt

用VHDL语言描述的用锁存器

; Fitter Aggressive Routability Optimizations        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                   ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining             ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
; Stop After Congestion Map Generation               ; Off                            ; Off                            ;
; Use smart compilation                              ; Off                            ; Off                            ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/singt/singt.pin.


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                               ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                         ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------+
; Total logic elements                        ; 10 / 12,060 ( < 1 % )                                                                         ;
;     -- Combinational with no register       ; 0                                                                                             ;
;     -- Register only                        ; 0                                                                                             ;
;     -- Combinational with a register        ; 10                                                                                            ;
;                                             ;                                                                                               ;
; Logic element usage by number of LUT inputs ;                                                                                               ;
;     -- 4 input functions                    ; 0                                                                                             ;
;     -- 3 input functions                    ; 0                                                                                             ;
;     -- 2 input functions                    ; 9                                                                                             ;
;     -- 1 input functions                    ; 1                                                                                             ;
;     -- 0 input functions                    ; 0                                                                                             ;
;                                             ;                                                                                               ;
; Logic elements by mode                      ;                                                                                               ;
;     -- normal mode                          ; 1                                                                                             ;
;     -- arithmetic mode                      ; 9                                                                                             ;
;     -- qfbk mode                            ; 0                                                                                             ;
;     -- register cascade mode                ; 0                                                                                             ;
;     -- synchronous clear/load mode          ; 0                                                                                             ;
;     -- asynchronous clear/load mode         ; 0                                                                                             ;
;                                             ;                                                                                               ;
; Total registers                             ; 10 / 12,567 ( < 1 % )                                                                         ;
; Total LABs                                  ; 1 / 1,206 ( < 1 % )                                                                           ;
; Logic elements in carry chains              ; 10                                                                                            ;
; User inserted logic elements                ; 0                                                                                             ;
; Virtual pins                                ; 0                                                                                             ;
; I/O pins                                    ; 11 / 173 ( 6 % )                                                                              ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )                                                                                ;
; Global signals                              ; 1                                                                                             ;
; M4Ks                                        ; 3 / 52 ( 6 % )                                                                                ;
; Total memory bits                           ; 10,240 / 239,616 ( 4 % )                                                                      ;
; Total RAM block bits                        ; 13,824 / 239,616 ( 6 % )                                                                      ;
; PLLs                                        ; 1 / 2 ( 50 % )                                                                                ;
; Global clocks                               ; 1 / 8 ( 13 % )                                                                                ;
; Average interconnect usage                  ; 0%                                                                                            ;
; Peak interconnect usage                     ; 0%                                                                                            ;
; Maximum fan-out node                        ; pll_w:inst1|altpll:altpll_component|_clk0                                                     ;
; Maximum fan-out                             ; 13                                                                                            ;
; Highest non-global fan-out signal           ; add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|counter_cella4~COUT ;
; Highest non-global fan-out                  ; 5                                                                                             ;
; Total fan-out                               ; 77                                                                                            ;
; Average fan-out                             ; 2.85                                                                                          ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                   ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; in_clk ; 28    ; 1        ; 0            ; 15           ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                   ;
+------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load  ;
+------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; sin_out[0] ; 208   ; 2        ; 26           ; 27           ; 2           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; Fitter               ; 10 pF ;
; sin_out[1] ; 88    ; 4        ; 18           ; 0            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; Fitter               ; 10 pF ;