singt.tan.rpt

用VHDL语言描述的用锁存器

+----------------------------------------------------------+----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+
; Worst-case tco                                           ; N/A      ; None                              ; 6.798 ns                         ; rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0]                          ; sin_out[0]                                                                          ; in_clk                                    ; --                                        ; 0            ;
; Clock Setup: 'pll_w:inst1|altpll:altpll_component|_clk0' ; 4.924 ns ; 100.00 MHz ( period = 10.000 ns ) ; 197.01 MHz ( period = 5.076 ns ) ; rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9 ; rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0]  ; pll_w:inst1|altpll:altpll_component|_clk0 ; pll_w:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'pll_w:inst1|altpll:altpll_component|_clk0'  ; 1.323 ns ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8]                         ; add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8] ; pll_w:inst1|altpll:altpll_component|_clk0 ; pll_w:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                             ;          ;                                   ;                                  ;                                                                                                             ;                                                                                     ;                                           ;                                           ; 0            ;
+----------------------------------------------------------+----------+-----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------+-------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                            ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll_w:inst1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; in_clk   ; 2                     ; 1                   ; -2.054 ns ;              ;
; in_clk                                    ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+