singt.tan.summary

用VHDL语言描述的用锁存器

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.798 ns
From           : rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0]
To             : sin_out[0]
From Clock     : in_clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'pll_w:inst1|altpll:altpll_component|_clk0'
Slack          : 4.924 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a1~porta_address_reg9
To             : rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0]
From Clock     : pll_w:inst1|altpll:altpll_component|_clk0
To Clock       : pll_w:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'pll_w:inst1|altpll:altpll_component|_clk0'
Slack          : 1.323 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8]
To             : add_count:inst2|lpm_counter:lpm_counter_component|cntr_jeh:auto_generated|safe_q[8]
From Clock     : pll_w:inst1|altpll:altpll_component|_clk0
To Clock       : pll_w:inst1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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