singt.fit.smsg

用VHDL语言描述的用锁存器

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 14 09:57:20 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off singt -c singt
Info: Selected device EP1C12Q240C8 for design "singt"
Info: Implementing parameter values for PLL "pll_w:inst1|altpll:altpll_component|pll"
    Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_w:inst1|altpll:altpll_component|_clk0 port
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 32 of 32 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6Q240C8 is compatible
Info: Fitter converted 2 user pins into dedicated programming pins
    Info: Pin ~nCSO~ is reserved at location 24
    Info: Pin ~ASDO~ is reserved at location 37
Warning: No exact pin location assignment(s) for 11 pins of 11 total pins
    Info: Pin sin_out[9] not assigned to an exact location on the device
    Info: Pin sin_out[8] not assigned to an exact location on the device
    Info: Pin sin_out[7] not assigned to an exact location on the device
    Info: Pin sin_out[6] not assigned to an exact location on the device
    Info: Pin sin_out[5] not assigned to an exact location on the device
    Info: Pin sin_out[4] not assigned to an exact location on the device
    Info: Pin sin_out[3] not assigned to an exact location on the device
    Info: Pin sin_out[2] not assigned to an exact location on the device
    Info: Pin sin_out[1] not assigned to an exact location on the device
    Info: Pin sin_out[0] not assigned to an exact location on the device
    Info: Pin in_clk not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Promoted PLL clock signals
    Info: Promoted signal "pll_w:inst1|altpll:altpll_component|_clk0" to use global clock (user assigned)
Info: Completed PLL Placement Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:01
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 10 (unused VREF, 3.30 VCCIO, 0 input, 10 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is memory to memory delay of 4.319 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y13; Fanout = 1; MEM Node = 'rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|ram_block1a9~porta_address_reg9'
    Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X19_Y13; Fanout = 1; MEM Node = 'rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[9]'
    Info: Total cell delay = 4.319 ns ( 100.00 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X10_Y0 to location X20_Y13
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 181 megabytes of memory during processing
    Info: Processing ended: Tue Apr 14 09:57:33 2009
    Info: Elapsed time: 00:00:13