shijinzhi.txt

EDA 十进制计数器、BCD VHDL源代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY counter IS
   PORT(clr,en,clk: IN STD_LOGIC;
        co        : OUT STD_LOGIC;       
        Q         : OUT STD_ULOGIC_VECTOR(3 DOWNTO 0);
		VGA       : OUT STD_ULOGIC_VECTOR(3 DOWNTO 0)
		);
END counter;

ARCHITECTURE counter1 OF counter IS
   SIGNAL qs: STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL ca: STD_ULOGIC;
BEGIN
	VGA <= "0001";
   PROCESS(clk)    
     VARIABLE q10:INTEGER;
   BEGIN
      IF(rising_edge(clk)) THEN
         IF(clr='1') THEN
            q10:=0;
         ELSIF(en='1') THEN
            IF(q10=9) THEN
               q10:=0;
               ca<='0';
            ELSIF(q10=8) THEN
               q10:=q10+1;
               ca<='1';
            ELSE
               q10:=q10+1;
               ca<='0';
            END IF;
         END IF;
      END IF;
      qs<=CONV_STD_LOGIC_VECTOR(q10,4);
      Q<= not TO_STDULOGICVECTOR(qs);	
   END PROCESS;

   co<= not (ca AND en);				

END counter1;