h_suber.tan.qmsg

EDA 全减器 包括半减器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 31 20:18:53 2009 " "Info: Processing started: Tue Mar 31 20:18:53 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off h_suber -c h_suber --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off h_suber -c h_suber --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "x s_out 8.577 ns Longest " "Info: Longest tpd from source pin \"x\" to destination pin \"s_out\" is 8.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns x 1 PIN PIN_W20 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W20; Fanout = 2; PIN Node = 'x'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { x } "NODE_NAME" } } { "h_suber.vhd" "" { Text "F:/EDA/全减器/h_suber.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.690 ns) + CELL(0.280 ns) 5.057 ns s_out~0 2 COMB LC_X1_Y1_N4 1 " "Info: 2: + IC(3.690 ns) + CELL(0.280 ns) = 5.057 ns; Loc. = LC_X1_Y1_N4; Fanout = 1; COMB Node = 's_out~0'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.970 ns" { x s_out~0 } "NODE_NAME" } } { "h_suber.vhd" "" { Text "F:/EDA/全减器/h_suber.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(2.404 ns) 8.577 ns s_out 3 PIN PIN_Y21 0 " "Info: 3: + IC(1.116 ns) + CELL(2.404 ns) = 8.577 ns; Loc. = PIN_Y21; Fanout = 0; PIN Node = 's_out'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.520 ns" { s_out~0 s_out } "NODE_NAME" } } { "h_suber.vhd" "" { Text "F:/EDA/全减器/h_suber.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.771 ns ( 43.97 % ) " "Info: Total cell delay = 3.771 ns ( 43.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.806 ns ( 56.03 % ) " "Info: Total interconnect delay = 4.806 ns ( 56.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.577 ns" { x s_out~0 s_out } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "8.577 ns" { x x~out0 s_out~0 s_out } { 0.000ns 0.000ns 3.690ns 1.116ns } { 0.000ns 1.087ns 0.280ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 31 20:18:53 2009 " "Info: Processing ended: Tue Mar 31 20:18:53 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}