h_suber.vhd

来自「EDA 全减器 包括半减器」· VHDL 代码 · 共 11 行

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY h_suber IS 
PORT(x,y: IN STD_LOGIC; 
diff,s_out:OUT STD_LOGIC); 
END h_suber; 
ARCHITECTURE behav OF h_suber IS 
BEGIN 
diff<=x XOR y; 
s_out<=(NOT x) AND y; 
END behav;