graycounter.tan.rpt

来自「TI公司的TLC5510的用VHDL写的控制器及其仿真」· RPT 代码 · 共 459 行 · 第 1/4 页

; N/A           ; None        ; -1.793 ns ; Enable_in ; BinaryCount[6]         ; clk      ;
; N/A           ; None        ; -1.879 ns ; Enable_in ; BinaryCount[7]         ; clk      ;
; N/A           ; None        ; -2.069 ns ; Enable_in ; BinaryCount[8]         ; clk      ;
; N/A           ; None        ; -2.155 ns ; Enable_in ; BinaryCount[9]         ; clk      ;
; N/A           ; None        ; -2.241 ns ; Enable_in ; BinaryCount[10]        ; clk      ;
; N/A           ; None        ; -2.327 ns ; Enable_in ; BinaryCount[11]        ; clk      ;
; N/A           ; None        ; -2.413 ns ; Enable_in ; BinaryCount[12]        ; clk      ;
+---------------+-------------+-----------+-----------+------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu May 07 08:52:17 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off GrayCounter -c GrayCounter --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 337.72 MHz between source register "BinaryCount[0]" and destination register "BinaryCount[12]" (period= 2.961 ns)
    Info: + Longest register to register delay is 2.697 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 3; REG Node = 'BinaryCount[0]'
        Info: 2: + IC(0.437 ns) + CELL(0.596 ns) = 1.033 ns; Loc. = LCCOMB_X31_Y15_N0; Fanout = 2; COMB Node = 'BinaryCount[0]~144'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.119 ns; Loc. = LCCOMB_X31_Y15_N2; Fanout = 2; COMB Node = 'BinaryCount[1]~146'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.205 ns; Loc. = LCCOMB_X31_Y15_N4; Fanout = 2; COMB Node = 'BinaryCount[2]~148'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.291 ns; Loc. = LCCOMB_X31_Y15_N6; Fanout = 2; COMB Node = 'BinaryCount[3]~150'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.377 ns; Loc. = LCCOMB_X31_Y15_N8; Fanout = 2; COMB Node = 'BinaryCount[4]~152'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.463 ns; Loc. = LCCOMB_X31_Y15_N10; Fanout = 2; COMB Node = 'BinaryCount[5]~154'
        Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.549 ns; Loc. = LCCOMB_X31_Y15_N12; Fanout = 2; COMB Node = 'BinaryCount[6]~156'
        Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 1.739 ns; Loc. = LCCOMB_X31_Y15_N14; Fanout = 2; COMB Node = 'BinaryCount[7]~158'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.825 ns; Loc. = LCCOMB_X31_Y15_N16; Fanout = 2; COMB Node = 'BinaryCount[8]~160'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 1.911 ns; Loc. = LCCOMB_X31_Y15_N18; Fanout = 2; COMB Node = 'BinaryCount[9]~162'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 1.997 ns; Loc. = LCCOMB_X31_Y15_N20; Fanout = 2; COMB Node = 'BinaryCount[10]~164'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.083 ns; Loc. = LCCOMB_X31_Y15_N22; Fanout = 1; COMB Node = 'BinaryCount[11]~166'
        Info: 14: + IC(0.000 ns) + CELL(0.506 ns) = 2.589 ns; Loc. = LCCOMB_X31_Y15_N24; Fanout = 1; COMB Node = 'BinaryCount[12]~167'
        Info: 15: + IC(0.000 ns) + CELL(0.108 ns) = 2.697 ns; Loc. = LCFF_X31_Y15_N25; Fanout = 3; REG Node = 'BinaryCount[12]'
        Info: Total cell delay = 2.260 ns ( 83.80 % )
        Info: Total interconnect delay = 0.437 ns ( 16.20 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.819 ns; Loc. = LCFF_X31_Y15_N25; Fanout = 3; REG Node = 'BinaryCount[12]'
            Info: Total cell delay = 1.756 ns ( 62.29 % )
            Info: Total interconnect delay = 1.063 ns ( 37.71 % )
        Info: - Longest clock path from clock "clk" to source register is 2.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.819 ns; Loc. = LCFF_X31_Y15_N1; Fanout = 3; REG Node = 'BinaryCount[0]'
            Info: Total cell delay = 1.756 ns ( 62.29 % )
            Info: Total interconnect delay = 1.063 ns ( 37.71 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "BinaryCount[12]" (data pin = "Enable_in", clock pin = "clk") is 2.679 ns
    Info: + Longest pin to register delay is 5.538 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_89; Fanout = 4; PIN Node = 'Enable_in'
        Info: 2: + IC(2.153 ns) + CELL(0.621 ns) = 3.874 ns; Loc. = LCCOMB_X31_Y15_N0; Fanout = 2; COMB Node = 'BinaryCount[0]~144'
        Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 3.960 ns; Loc. = LCCOMB_X31_Y15_N2; Fanout = 2; COMB Node = 'BinaryCount[1]~146'
        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 4.046 ns; Loc. = LCCOMB_X31_Y15_N4; Fanout = 2; COMB Node = 'BinaryCount[2]~148'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 4.132 ns; Loc. = LCCOMB_X31_Y15_N6; Fanout = 2; COMB Node = 'BinaryCount[3]~150'
        Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 4.218 ns; Loc. = LCCOMB_X31_Y15_N8; Fanout = 2; COMB Node = 'BinaryCount[4]~152'
        Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 4.304 ns; Loc. = LCCOMB_X31_Y15_N10; Fanout = 2; COMB Node = 'BinaryCount[5]~154'
        Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 4.390 ns; Loc. = LCCOMB_X31_Y15_N12; Fanout = 2; COMB Node = 'BinaryCount[6]~156'
        Info: 9: + IC(0.000 ns) + CELL(0.190 ns) = 4.580 ns; Loc. = LCCOMB_X31_Y15_N14; Fanout = 2; COMB Node = 'BinaryCount[7]~158'
        Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 4.666 ns; Loc. = LCCOMB_X31_Y15_N16; Fanout = 2; COMB Node = 'BinaryCount[8]~160'
        Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 4.752 ns; Loc. = LCCOMB_X31_Y15_N18; Fanout = 2; COMB Node = 'BinaryCount[9]~162'
        Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 4.838 ns; Loc. = LCCOMB_X31_Y15_N20; Fanout = 2; COMB Node = 'BinaryCount[10]~164'
        Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 4.924 ns; Loc. = LCCOMB_X31_Y15_N22; Fanout = 1; COMB Node = 'BinaryCount[11]~166'
        Info: 14: + IC(0.000 ns) + CELL(0.506 ns) = 5.430 ns; Loc. = LCCOMB_X31_Y15_N24; Fanout = 1; COMB Node = 'BinaryCount[12]~167'
        Info: 15: + IC(0.000 ns) + CELL(0.108 ns) = 5.538 ns; Loc. = LCFF_X31_Y15_N25; Fanout = 3; REG Node = 'BinaryCount[12]'
        Info: Total cell delay = 3.385 ns ( 61.12 % )
        Info: Total interconnect delay = 2.153 ns ( 38.88 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.819 ns; Loc. = LCFF_X31_Y15_N25; Fanout = 3; REG Node = 'BinaryCount[12]'
        Info: Total cell delay = 1.756 ns ( 62.29 % )
        Info: Total interconnect delay = 1.063 ns ( 37.71 % )
Info: tco from clock "clk" to destination pin "GrayCount_out[11]" through register "GrayCount_out[11]~reg0" is 8.614 ns
    Info: + Longest clock path from clock "clk" to source register is 2.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.819 ns; Loc. = LCFF_X30_Y15_N23; Fanout = 1; REG Node = 'GrayCount_out[11]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.29 % )
        Info: Total interconnect delay = 1.063 ns ( 37.71 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.491 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y15_N23; Fanout = 1; REG Node = 'GrayCount_out[11]~reg0'
        Info: 2: + IC(2.255 ns) + CELL(3.236 ns) = 5.491 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'GrayCount_out[11]'
        Info: Total cell delay = 3.236 ns ( 58.93 % )
        Info: Total interconnect delay = 2.255 ns ( 41.07 % )
Info: th for register "GrayCount_out[12]~reg0" (data pin = "Enable_in", clock pin = "clk") is -0.076 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.819 ns; Loc. = LCFF_X31_Y15_N29; Fanout = 2; REG Node = 'GrayCount_out[12]~reg0'
        Info: Total cell delay = 1.756 ns ( 62.29 % )
        Info: Total interconnect delay = 1.063 ns ( 37.71 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 3.201 ns
        Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_89; Fanout = 4; PIN Node = 'Enable_in'
        Info: 2: + IC(1.787 ns) + CELL(0.206 ns) = 3.093 ns; Loc. = LCCOMB_X31_Y15_N28; Fanout = 1; COMB Node = 'GrayCount_out[12]~517'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.201 ns; Loc. = LCFF_X31_Y15_N29; Fanout = 2; REG Node = 'GrayCount_out[12]~reg0'
        Info: Total cell delay = 1.414 ns ( 44.17 % )
        Info: Total interconnect delay = 1.787 ns ( 55.83 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Thu May 07 08:52:17 2009
    Info: Elapsed time: 00:00:00