prev_cmp_jsq.tan.qmsg

来自「TI公司的TLC5510的用VHDL写的控制器及其仿真」· QMSG 代码 · 共 10 行 · 第 1/3 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register DATA\[10\] register DATA\[0\] 182.85 MHz 5.469 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 182.85 MHz between source register \"DATA\[10\]\" and destination register \"DATA\[0\]\" (period= 5.469 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.205 ns + Longest register register " "Info: + Longest register to register delay is 5.205 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATA\[10\] 1 REG LCFF_X14_Y11_N21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N21; Fanout = 4; REG Node = 'DATA\[10\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[10] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.137 ns) + CELL(0.534 ns) 1.671 ns OUT1~294 2 COMB LCCOMB_X13_Y11_N16 1 " "Info: 2: + IC(1.137 ns) + CELL(0.534 ns) = 1.671 ns; Loc. = LCCOMB_X13_Y11_N16; Fanout = 1; COMB Node = 'OUT1~294'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.671 ns" { DATA[10] OUT1~294 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.615 ns) 2.681 ns OUT1~295 3 COMB LCCOMB_X13_Y11_N6 2 " "Info: 3: + IC(0.395 ns) + CELL(0.615 ns) = 2.681 ns; Loc. = LCCOMB_X13_Y11_N6; Fanout = 2; COMB Node = 'OUT1~295'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.010 ns" { OUT1~294 OUT1~295 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 3.249 ns LessThan0~151 4 COMB LCCOMB_X13_Y11_N0 2 " "Info: 4: + IC(0.362 ns) + CELL(0.206 ns) = 3.249 ns; Loc. = LCCOMB_X13_Y11_N0; Fanout = 2; COMB Node = 'LessThan0~151'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { OUT1~295 LessThan0~151 } "NODE_NAME" } } { "g:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "g:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1621 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 3.820 ns DATA\[0\]~495 5 COMB LCCOMB_X13_Y11_N14 16 " "Info: 5: + IC(0.365 ns) + CELL(0.206 ns) = 3.820 ns; Loc. = LCCOMB_X13_Y11_N14; Fanout = 16; COMB Node = 'DATA\[0\]~495'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { LessThan0~151 DATA[0]~495 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.855 ns) 5.205 ns DATA\[0\] 6 REG LCFF_X14_Y11_N1 5 " "Info: 6: + IC(0.530 ns) + CELL(0.855 ns) = 5.205 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA\[0\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { DATA[0]~495 DATA[0] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.416 ns ( 46.42 % ) " "Info: Total cell delay = 2.416 ns ( 46.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.789 ns ( 53.58 % ) " "Info: Total interconnect delay = 2.789 ns ( 53.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.205 ns" { DATA[10] OUT1~294 OUT1~295 LessThan0~151 DATA[0]~495 DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "5.205 ns" { DATA[10] {} OUT1~294 {} OUT1~295 {} LessThan0~151 {} DATA[0]~495 {} DATA[0] {} } { 0.000ns 1.137ns 0.395ns 0.362ns 0.365ns 0.530ns } { 0.000ns 0.534ns 0.615ns 0.206ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.788 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns CLK~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 2.788 ns DATA\[0\] 3 REG LCFF_X14_Y11_N1 5 " "Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA\[0\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { CLK~clkctrl DATA[0] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.98 % ) " "Info: Total cell delay = 1.756 ns ( 62.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.032 ns ( 37.02 % ) " "Info: Total interconnect delay = 1.032 ns ( 37.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[0] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.788 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns CLK~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 2.788 ns DATA\[10\] 3 REG LCFF_X14_Y11_N21 4 " "Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N21; Fanout = 4; REG Node = 'DATA\[10\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { CLK~clkctrl DATA[10] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.98 % ) " "Info: Total cell delay = 1.756 ns ( 62.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.032 ns ( 37.02 % ) " "Info: Total interconnect delay = 1.032 ns ( 37.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[10] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[10] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[0] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[10] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[10] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.205 ns" { DATA[10] OUT1~294 OUT1~295 LessThan0~151 DATA[0]~495 DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "5.205 ns" { DATA[10] {} OUT1~294 {} OUT1~295 {} LessThan0~151 {} DATA[0]~495 {} DATA[0] {} } { 0.000ns 1.137ns 0.395ns 0.362ns 0.365ns 0.530ns } { 0.000ns 0.534ns 0.615ns 0.206ns 0.206ns 0.855ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[0] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[10] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[10] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DATA\[0\] EN CLK 6.743 ns register " "Info: tsu for register \"DATA\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 6.743 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.571 ns + Longest pin register " "Info: + Longest pin to register delay is 9.571 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns EN 1 PIN PIN_126 2 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_126; Fanout = 2; PIN Node = 'EN'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.628 ns) + CELL(0.624 ns) 8.186 ns DATA\[0\]~495 2 COMB LCCOMB_X13_Y11_N14 16 " "Info: 2: + IC(6.628 ns) + CELL(0.624 ns) = 8.186 ns; Loc. = LCCOMB_X13_Y11_N14; Fanout = 16; COMB Node = 'DATA\[0\]~495'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.252 ns" { EN DATA[0]~495 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.855 ns) 9.571 ns DATA\[0\] 3 REG LCFF_X14_Y11_N1 5 " "Info: 3: + IC(0.530 ns) + CELL(0.855 ns) = 9.571 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA\[0\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { DATA[0]~495 DATA[0] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.413 ns ( 25.21 % ) " "Info: Total cell delay = 2.413 ns ( 25.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.158 ns ( 74.79 % ) " "Info: Total interconnect delay = 7.158 ns ( 74.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.571 ns" { EN DATA[0]~495 DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "9.571 ns" { EN {} EN~combout {} DATA[0]~495 {} DATA[0] {} } { 0.000ns 0.000ns 6.628ns 0.530ns } { 0.000ns 0.934ns 0.624ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.788 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns CLK~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 2.788 ns DATA\[0\] 3 REG LCFF_X14_Y11_N1 5 " "Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N1; Fanout = 5; REG Node = 'DATA\[0\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { CLK~clkctrl DATA[0] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.98 % ) " "Info: Total cell delay = 1.756 ns ( 62.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.032 ns ( 37.02 % ) " "Info: Total interconnect delay = 1.032 ns ( 37.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[0] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.571 ns" { EN DATA[0]~495 DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "9.571 ns" { EN {} EN~combout {} DATA[0]~495 {} DATA[0] {} } { 0.000ns 0.000ns 6.628ns 0.530ns } { 0.000ns 0.934ns 0.624ns 0.855ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[0] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[0] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK INDATA\[7\] DATA\[7\] 9.257 ns register " "Info: tco from clock \"CLK\" to destination pin \"INDATA\[7\]\" through register \"DATA\[7\]\" is 9.257 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.788 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns CLK~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 2.788 ns DATA\[7\] 3 REG LCFF_X14_Y11_N15 4 " "Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X14_Y11_N15; Fanout = 4; REG Node = 'DATA\[7\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { CLK~clkctrl DATA[7] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.98 % ) " "Info: Total cell delay = 1.756 ns ( 62.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.032 ns ( 37.02 % ) " "Info: Total interconnect delay = 1.032 ns ( 37.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[7] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[7] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.165 ns + Longest register pin " "Info: + Longest register to pin delay is 6.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DATA\[7\] 1 REG LCFF_X14_Y11_N15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N15; Fanout = 4; REG Node = 'DATA\[7\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { DATA[7] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.949 ns) + CELL(3.216 ns) 6.165 ns INDATA\[7\] 2 PIN PIN_118 0 " "Info: 2: + IC(2.949 ns) + CELL(3.216 ns) = 6.165 ns; Loc. = PIN_118; Fanout = 0; PIN Node = 'INDATA\[7\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { DATA[7] INDATA[7] } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.216 ns ( 52.17 % ) " "Info: Total cell delay = 3.216 ns ( 52.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.949 ns ( 47.83 % ) " "Info: Total interconnect delay = 2.949 ns ( 47.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { DATA[7] INDATA[7] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "6.165 ns" { DATA[7] {} INDATA[7] {} } { 0.000ns 2.949ns } { 0.000ns 3.216ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl DATA[7] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DATA[7] {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.165 ns" { DATA[7] INDATA[7] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "6.165 ns" { DATA[7] {} INDATA[7] {} } { 0.000ns 2.949ns } { 0.000ns 3.216ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "OUT1~reg0 CLR CLK -0.762 ns register " "Info: th for register \"OUT1~reg0\" (data pin = \"CLR\", clock pin = \"CLK\") is -0.762 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.788 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns CLK~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLK~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.666 ns) 2.788 ns OUT1~reg0 3 REG LCFF_X13_Y11_N9 2 " "Info: 3: + IC(0.893 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X13_Y11_N9; Fanout = 2; REG Node = 'OUT1~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.559 ns" { CLK~clkctrl OUT1~reg0 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.98 % ) " "Info: Total cell delay = 1.756 ns ( 62.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.032 ns ( 37.02 % ) " "Info: Total interconnect delay = 1.032 ns ( 37.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl OUT1~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} OUT1~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.856 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns CLR 1 PIN PIN_18 2 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_18; Fanout = 2; PIN Node = 'CLR'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLR } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.585 ns) + CELL(0.505 ns) 3.180 ns OUT1~296 2 COMB LCCOMB_X13_Y11_N18 1 " "Info: 2: + IC(1.585 ns) + CELL(0.505 ns) = 3.180 ns; Loc. = LCCOMB_X13_Y11_N18; Fanout = 1; COMB Node = 'OUT1~296'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.090 ns" { CLR OUT1~296 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 3.748 ns OUT1~297 3 COMB LCCOMB_X13_Y11_N8 1 " "Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 3.748 ns; Loc. = LCCOMB_X13_Y11_N8; Fanout = 1; COMB Node = 'OUT1~297'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { OUT1~296 OUT1~297 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.856 ns OUT1~reg0 4 REG LCFF_X13_Y11_N9 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.856 ns; Loc. = LCFF_X13_Y11_N9; Fanout = 2; REG Node = 'OUT1~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { OUT1~297 OUT1~reg0 } "NODE_NAME" } } { "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/ledlight/jsq.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.909 ns ( 49.51 % ) " "Info: Total cell delay = 1.909 ns ( 49.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.947 ns ( 50.49 % ) " "Info: Total interconnect delay = 1.947 ns ( 50.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.856 ns" { CLR OUT1~296 OUT1~297 OUT1~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.856 ns" { CLR {} CLR~combout {} OUT1~296 {} OUT1~297 {} OUT1~reg0 {} } { 0.000ns 0.000ns 1.585ns 0.362ns 0.000ns } { 0.000ns 1.090ns 0.505ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { CLK CLK~clkctrl OUT1~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { CLK {} CLK~combout {} CLK~clkctrl {} OUT1~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.893ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.856 ns" { CLR OUT1~296 OUT1~297 OUT1~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.856 ns" { CLR {} CLR~combout {} OUT1~296 {} OUT1~297 {} OUT1~reg0 {} } { 0.000ns 0.000ns 1.585ns 0.362ns 0.000ns } { 0.000ns 1.090ns 0.505ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}