prev_cmp_graycounter.tan.qmsg

来自「TI公司的TLC5510的用VHDL写的控制器及其仿真」· QMSG 代码 · 共 10 行 · 第 1/4 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk GrayCount_out\[11\] GrayCount_out\[11\]~reg0 8.614 ns register " "Info: tco from clock \"clk\" to destination pin \"GrayCount_out\[11\]\" through register \"GrayCount_out\[11\]~reg0\" is 8.614 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.666 ns) 2.819 ns GrayCount_out\[11\]~reg0 3 REG LCFF_X30_Y15_N23 1 " "Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.819 ns; Loc. = LCFF_X30_Y15_N23; Fanout = 1; REG Node = 'GrayCount_out\[11\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { clk~clkctrl GrayCount_out[11]~reg0 } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.29 % ) " "Info: Total cell delay = 1.756 ns ( 62.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.063 ns ( 37.71 % ) " "Info: Total interconnect delay = 1.063 ns ( 37.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.819 ns" { clk clk~clkctrl GrayCount_out[11]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.819 ns" { clk {} clk~combout {} clk~clkctrl {} GrayCount_out[11]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.924ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.491 ns + Longest register pin " "Info: + Longest register to pin delay is 5.491 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns GrayCount_out\[11\]~reg0 1 REG LCFF_X30_Y15_N23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y15_N23; Fanout = 1; REG Node = 'GrayCount_out\[11\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { GrayCount_out[11]~reg0 } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.255 ns) + CELL(3.236 ns) 5.491 ns GrayCount_out\[11\] 2 PIN PIN_64 0 " "Info: 2: + IC(2.255 ns) + CELL(3.236 ns) = 5.491 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'GrayCount_out\[11\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.491 ns" { GrayCount_out[11]~reg0 GrayCount_out[11] } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 58.93 % ) " "Info: Total cell delay = 3.236 ns ( 58.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.255 ns ( 41.07 % ) " "Info: Total interconnect delay = 2.255 ns ( 41.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.491 ns" { GrayCount_out[11]~reg0 GrayCount_out[11] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "5.491 ns" { GrayCount_out[11]~reg0 {} GrayCount_out[11] {} } { 0.000ns 2.255ns } { 0.000ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.819 ns" { clk clk~clkctrl GrayCount_out[11]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.819 ns" { clk {} clk~combout {} clk~clkctrl {} GrayCount_out[11]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.924ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.491 ns" { GrayCount_out[11]~reg0 GrayCount_out[11] } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "5.491 ns" { GrayCount_out[11]~reg0 {} GrayCount_out[11] {} } { 0.000ns 2.255ns } { 0.000ns 3.236ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "GrayCount_out\[12\]~reg0 Enable_in clk -0.076 ns register " "Info: th for register \"GrayCount_out\[12\]~reg0\" (data pin = \"Enable_in\", clock pin = \"clk\") is -0.076 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.229 ns clk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.229 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'clk~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.666 ns) 2.819 ns GrayCount_out\[12\]~reg0 3 REG LCFF_X31_Y15_N29 2 " "Info: 3: + IC(0.924 ns) + CELL(0.666 ns) = 2.819 ns; Loc. = LCFF_X31_Y15_N29; Fanout = 2; REG Node = 'GrayCount_out\[12\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { clk~clkctrl GrayCount_out[12]~reg0 } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 62.29 % ) " "Info: Total cell delay = 1.756 ns ( 62.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.063 ns ( 37.71 % ) " "Info: Total interconnect delay = 1.063 ns ( 37.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.819 ns" { clk clk~clkctrl GrayCount_out[12]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.819 ns" { clk {} clk~combout {} clk~clkctrl {} GrayCount_out[12]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.924ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.201 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.201 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns Enable_in 1 PIN PIN_89 4 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_89; Fanout = 4; PIN Node = 'Enable_in'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { Enable_in } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.787 ns) + CELL(0.206 ns) 3.093 ns GrayCount_out\[12\]~517 2 COMB LCCOMB_X31_Y15_N28 1 " "Info: 2: + IC(1.787 ns) + CELL(0.206 ns) = 3.093 ns; Loc. = LCCOMB_X31_Y15_N28; Fanout = 1; COMB Node = 'GrayCount_out\[12\]~517'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.993 ns" { Enable_in GrayCount_out[12]~517 } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.201 ns GrayCount_out\[12\]~reg0 3 REG LCFF_X31_Y15_N29 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.201 ns; Loc. = LCFF_X31_Y15_N29; Fanout = 2; REG Node = 'GrayCount_out\[12\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { GrayCount_out[12]~517 GrayCount_out[12]~reg0 } "NODE_NAME" } } { "GrayCounter.vhd" "" { Text "G:/altera/quartus/tlc5510/GrayCounter.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.414 ns ( 44.17 % ) " "Info: Total cell delay = 1.414 ns ( 44.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.787 ns ( 55.83 % ) " "Info: Total interconnect delay = 1.787 ns ( 55.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.201 ns" { Enable_in GrayCount_out[12]~517 GrayCount_out[12]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.201 ns" { Enable_in {} Enable_in~combout {} GrayCount_out[12]~517 {} GrayCount_out[12]~reg0 {} } { 0.000ns 0.000ns 1.787ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.819 ns" { clk clk~clkctrl GrayCount_out[12]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "2.819 ns" { clk {} clk~combout {} clk~clkctrl {} GrayCount_out[12]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.924ns } { 0.000ns 1.090ns 0.000ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.201 ns" { Enable_in GrayCount_out[12]~517 GrayCount_out[12]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.201 ns" { Enable_in {} Enable_in~combout {} GrayCount_out[12]~517 {} GrayCount_out[12]~reg0 {} } { 0.000ns 0.000ns 1.787ns 0.000ns } { 0.000ns 1.100ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 07 08:52:17 2009 " "Info: Processing ended: Thu May 07 08:52:17 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}