prev_cmp_sxh.fit.qmsg

来自「TI公司的TLC5510的用VHDL写的控制器及其仿真」· QMSG 代码 · 共 44 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 10:07:46 2009 " "Info: Processing started: Mon May 04 10:07:46 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off SXH -c SXH " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SXH -c SXH" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "SXH EP2S15F484C3 " "Info: Automatically selected device EP2S15F484C3 for design SXH" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "altpll:altpll_component\|pll Enhanced " "Info: Implemented PLL \"altpll:altpll_component\|pll\" as Enhanced PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:altpll_component\|_clk0 1 439 0 0 " "Info: Implementing clock multiplication of 1, clock division of 439, and phase shift of 0 degrees (0 ps) for altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "g:/altera/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:altpll_component\|_clk1 1 4 0 0 " "Info: Implementing clock multiplication of 1, clock division of 4, and phase shift of 0 degrees (0 ps) for altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "g:/altera/quartus/libraries/megafunctions/altpll.tdf" 892 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "g:/altera/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "7 Top " "Info: Previous placement does not exist for 7 of 7 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S30F484C3 " "Info: Device EP2S30F484C3 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S60F484C3 " "Info: Device EP2S60F484C3 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S60F484C3ES " "Info: Device EP2S60F484C3ES is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" {  } { { "g:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "6 6 " "Warning: No exact pin location assignment(s) for 6 pins of 6 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "c0 " "Info: Pin c0 not assigned to an exact location on the device" {  } { { "g:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/quartus/bin/pin_planner.ppl" { c0 } } } { "SXH.vhd" "" { Text "G:/altera/quartus/tlc5510/SXH.vhd" 48 -1 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { c0 } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { c0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "c1 " "Info: Pin c1 not assigned to an exact location on the device" {  } { { "g:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/quartus/bin/pin_planner.ppl" { c1 } } } { "SXH.vhd" "" { Text "G:/altera/quartus/tlc5510/SXH.vhd" 49 -1 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { c1 } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { c1 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "locked " "Info: Pin locked not assigned to an exact location on the device" {  } { { "g:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/quartus/bin/pin_planner.ppl" { locked } } } { "SXH.vhd" "" { Text "G:/altera/quartus/tlc5510/SXH.vhd" 50 -1 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { locked } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { locked } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pllena " "Info: Pin pllena not assigned to an exact location on the device" {  } { { "g:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/quartus/bin/pin_planner.ppl" { pllena } } } { "SXH.vhd" "" { Text "G:/altera/quartus/tlc5510/SXH.vhd" 47 -1 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { pllena } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { pllena } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "areset " "Info: Pin areset not assigned to an exact location on the device" {  } { { "g:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/quartus/bin/pin_planner.ppl" { areset } } } { "SXH.vhd" "" { Text "G:/altera/quartus/tlc5510/SXH.vhd" 45 -1 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { areset } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { areset } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "inclk0 " "Info: Pin inclk0 not assigned to an exact location on the device" {  } { { "g:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/quartus/bin/pin_planner.ppl" { inclk0 } } } { "SXH.vhd" "" { Text "G:/altera/quartus/tlc5510/SXH.vhd" 46 -1 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altpll:altpll_component\|_clk0 (placed in counter C1 of PLL_6) " "Info: Automatically promoted node altpll:altpll_component\|_clk0 (placed in counter C1 of PLL_6)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_X21_Y0_N9 " "Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X21_Y0_N9" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "g:/altera/quartus/libraries/megafunctions/altpll.tdf" 518 3 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altpll:altpll_component\|_clk1 (placed in counter C2 of PLL_6) " "Info: Automatically promoted node altpll:altpll_component\|_clk1 (placed in counter C2 of PLL_6)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_X21_Y0_N7 " "Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X21_Y0_N7" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "g:/altera/quartus/libraries/megafunctions/altpll.tdf" 518 3 0 } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "" 0}