prev_cmp_tlc5510.qmsg

来自「TI公司的TLC5510的用VHDL写的控制器及其仿真」· QMSG 代码 · 共 62 行 · 第 1/5 页

{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 09 12:21:13 2009 " "Info: Processing ended: Thu Apr 09 12:21:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 09 12:21:14 2009 " "Info: Processing started: Thu Apr 09 12:21:14 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off tlc5510 -c tlc5510 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tlc5510 -c tlc5510 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 6 -1 0 } } { "g:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "STA_G_CURRENTSTATE " "Info: Detected ripple clock \"STA_G_CURRENTSTATE\" as buffer" {  } { { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } } { "g:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "STA_G_CURRENTSTATE" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register STA_G_CURRENTSTATE STA_G_CURRENTSTATE 360.1 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 360.1 MHz between source register \"STA_G_CURRENTSTATE\" and destination register \"STA_G_CURRENTSTATE\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Longest register register " "Info: + Longest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STA_G_CURRENTSTATE 1 REG LCFF_X1_Y6_N21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { STA_G_CURRENTSTATE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns STA_G_CURRENTSTATE~2 2 COMB LCCOMB_X1_Y6_N20 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X1_Y6_N20; Fanout = 1; COMB Node = 'STA_G_CURRENTSTATE~2'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { STA_G_CURRENTSTATE STA_G_CURRENTSTATE~2 } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns STA_G_CURRENTSTATE 3 REG LCFF_X1_Y6_N21 4 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { STA_G_CURRENTSTATE~2 STA_G_CURRENTSTATE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { STA_G_CURRENTSTATE STA_G_CURRENTSTATE~2 STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { STA_G_CURRENTSTATE {} STA_G_CURRENTSTATE~2 {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.554 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns CLK 1 CLK PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.666 ns) 3.554 ns STA_G_CURRENTSTATE 2 REG LCFF_X1_Y6_N21 4 " "Info: 2: + IC(1.943 ns) + CELL(0.666 ns) = 3.554 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.609 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.611 ns ( 45.33 % ) " "Info: Total cell delay = 1.611 ns ( 45.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.943 ns ( 54.67 % ) " "Info: Total interconnect delay = 1.943 ns ( 54.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.554 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.554 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.945ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.554 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.554 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns CLK 1 CLK PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.666 ns) 3.554 ns STA_G_CURRENTSTATE 2 REG LCFF_X1_Y6_N21 4 " "Info: 2: + IC(1.943 ns) + CELL(0.666 ns) = 3.554 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.609 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.611 ns ( 45.33 % ) " "Info: Total cell delay = 1.611 ns ( 45.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.943 ns ( 54.67 % ) " "Info: Total interconnect delay = 1.943 ns ( 54.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.554 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.554 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.945ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.554 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.554 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.945ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.554 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.554 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.945ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { STA_G_CURRENTSTATE STA_G_CURRENTSTATE~2 STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { STA_G_CURRENTSTATE {} STA_G_CURRENTSTATE~2 {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.554 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.554 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.945ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.554 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "3.554 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.945ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { STA_G_CURRENTSTATE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { STA_G_CURRENTSTATE {} } {  } {  } "" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DATA\[0\]~reg0 D\[0\] CLK 1.402 ns register " "Info: tsu for register \"DATA\[0\]~reg0\" (data pin = \"D\[0\]\", clock pin = \"CLK\") is 1.402 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.640 ns + Longest pin register " "Info: + Longest pin to register delay is 7.640 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns D\[0\] 1 PIN PIN_104 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_104; Fanout = 1; PIN Node = 'D\[0\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[0] } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.381 ns) + CELL(0.206 ns) 7.532 ns DATA\[0\]~reg0feeder 2 COMB LCCOMB_X13_Y13_N20 1 " "Info: 2: + IC(6.381 ns) + CELL(0.206 ns) = 7.532 ns; Loc. = LCCOMB_X13_Y13_N20; Fanout = 1; COMB Node = 'DATA\[0\]~reg0feeder'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.587 ns" { D[0] DATA[0]~reg0feeder } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.640 ns DATA\[0\]~reg0 3 REG LCFF_X13_Y13_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.640 ns; Loc. = LCFF_X13_Y13_N21; Fanout = 1; REG Node = 'DATA\[0\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { DATA[0]~reg0feeder DATA[0]~reg0 } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 47 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.259 ns ( 16.48 % ) " "Info: Total cell delay = 1.259 ns ( 16.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.381 ns ( 83.52 % ) " "Info: Total interconnect delay = 6.381 ns ( 83.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.640 ns" { D[0] DATA[0]~reg0feeder DATA[0]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "7.640 ns" { D[0] {} D[0]~combout {} DATA[0]~reg0feeder {} DATA[0]~reg0 {} } { 0.000ns 0.000ns 6.381ns 0.000ns } { 0.000ns 0.945ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 47 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.198 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 6.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns CLK 1 CLK PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.970 ns) 3.858 ns STA_G_CURRENTSTATE 2 REG LCFF_X1_Y6_N21 4 " "Info: 2: + IC(1.943 ns) + CELL(0.970 ns) = 3.858 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 4.675 ns STA_G_CURRENTSTATE~clkctrl 3 COMB CLKCTRL_G1 8 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 4.675 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'STA_G_CURRENTSTATE~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { STA_G_CURRENTSTATE STA_G_CURRENTSTATE~clkctrl } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.857 ns) + CELL(0.666 ns) 6.198 ns DATA\[0\]~reg0 4 REG LCFF_X13_Y13_N21 1 " "Info: 4: + IC(0.857 ns) + CELL(0.666 ns) = 6.198 ns; Loc. = LCFF_X13_Y13_N21; Fanout = 1; REG Node = 'DATA\[0\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { STA_G_CURRENTSTATE~clkctrl DATA[0]~reg0 } "NODE_NAME" } } { "tlc5510.vhd" "" {