tlc5510.tan.qmsg

来自「TI公司的TLC5510的用VHDL写的控制器及其仿真」· QMSG 代码 · 共 12 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TPD_RESULT" "CTLOE ADOE 10.532 ns Longest " "Info: Longest tpd from source pin \"CTLOE\" to destination pin \"ADOE\" is 10.532 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns CTLOE 1 PIN PIN_132 1 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_132; Fanout = 1; PIN Node = 'CTLOE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CTLOE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.352 ns) + CELL(3.236 ns) 10.532 ns ADOE 2 PIN PIN_133 0 " "Info: 2: + IC(6.352 ns) + CELL(3.236 ns) = 10.532 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'ADOE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.588 ns" { CTLOE ADOE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.180 ns ( 39.69 % ) " "Info: Total cell delay = 4.180 ns ( 39.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.352 ns ( 60.31 % ) " "Info: Total interconnect delay = 6.352 ns ( 60.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.532 ns" { CTLOE ADOE } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "10.532 ns" { CTLOE {} CTLOE~combout {} ADOE {} } { 0.000ns 0.000ns 6.352ns } { 0.000ns 0.944ns 3.236ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "DATA\[7\]~reg0 D\[7\] CLK 4.490 ns register " "Info: th for register \"DATA\[7\]~reg0\" (data pin = \"D\[7\]\", clock pin = \"CLK\") is 4.490 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.170 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 6.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns CLK 1 CLK PIN_86 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_86; Fanout = 1; CLK Node = 'CLK'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.970 ns) 3.858 ns STA_G_CURRENTSTATE 2 REG LCFF_X1_Y6_N21 4 " "Info: 2: + IC(1.943 ns) + CELL(0.970 ns) = 3.858 ns; Loc. = LCFF_X1_Y6_N21; Fanout = 4; REG Node = 'STA_G_CURRENTSTATE'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { CLK STA_G_CURRENTSTATE } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 4.675 ns STA_G_CURRENTSTATE~clkctrl 3 COMB CLKCTRL_G1 8 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 4.675 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'STA_G_CURRENTSTATE~clkctrl'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { STA_G_CURRENTSTATE STA_G_CURRENTSTATE~clkctrl } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.666 ns) 6.170 ns DATA\[7\]~reg0 4 REG LCFF_X27_Y7_N1 1 " "Info: 4: + IC(0.829 ns) + CELL(0.666 ns) = 6.170 ns; Loc. = LCFF_X27_Y7_N1; Fanout = 1; REG Node = 'DATA\[7\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { STA_G_CURRENTSTATE~clkctrl DATA[7]~reg0 } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 47 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.581 ns ( 41.83 % ) " "Info: Total cell delay = 2.581 ns ( 41.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.589 ns ( 58.17 % ) " "Info: Total interconnect delay = 3.589 ns ( 58.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.170 ns" { CLK STA_G_CURRENTSTATE STA_G_CURRENTSTATE~clkctrl DATA[7]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "6.170 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} STA_G_CURRENTSTATE~clkctrl {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 1.943ns 0.817ns 0.829ns } { 0.000ns 0.945ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 47 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.986 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns D\[7\] 1 PIN PIN_90 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_90; Fanout = 1; PIN Node = 'D\[7\]'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { D[7] } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.206 ns) 1.878 ns DATA\[7\]~reg0feeder 2 COMB LCCOMB_X27_Y7_N0 1 " "Info: 2: + IC(0.562 ns) + CELL(0.206 ns) = 1.878 ns; Loc. = LCCOMB_X27_Y7_N0; Fanout = 1; COMB Node = 'DATA\[7\]~reg0feeder'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.768 ns" { D[7] DATA[7]~reg0feeder } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.986 ns DATA\[7\]~reg0 3 REG LCFF_X27_Y7_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.986 ns; Loc. = LCFF_X27_Y7_N1; Fanout = 1; REG Node = 'DATA\[7\]~reg0'" {  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { DATA[7]~reg0feeder DATA[7]~reg0 } "NODE_NAME" } } { "tlc5510.vhd" "" { Text "G:/altera/quartus/tlc5510/tlc5510.vhd" 47 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.424 ns ( 71.70 % ) " "Info: Total cell delay = 1.424 ns ( 71.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.562 ns ( 28.30 % ) " "Info: Total interconnect delay = 0.562 ns ( 28.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.986 ns" { D[7] DATA[7]~reg0feeder DATA[7]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "1.986 ns" { D[7] {} D[7]~combout {} DATA[7]~reg0feeder {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.562ns 0.000ns } { 0.000ns 1.110ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.170 ns" { CLK STA_G_CURRENTSTATE STA_G_CURRENTSTATE~clkctrl DATA[7]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "6.170 ns" { CLK {} CLK~combout {} STA_G_CURRENTSTATE {} STA_G_CURRENTSTATE~clkctrl {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 1.943ns 0.817ns 0.829ns } { 0.000ns 0.945ns 0.970ns 0.000ns 0.666ns } "" } } { "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.986 ns" { D[7] DATA[7]~reg0feeder DATA[7]~reg0 } "NODE_NAME" } } { "g:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/quartus/bin/Technology_Viewer.qrui" "1.986 ns" { D[7] {} D[7]~combout {} DATA[7]~reg0feeder {} DATA[7]~reg0 {} } { 0.000ns 0.000ns 0.562ns 0.000ns } { 0.000ns 1.110ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 11:08:12 2009 " "Info: Processing ended: Mon May 04 11:08:12 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}