tlc5510.vhd

TI公司的TLC5510的用VHDL写的控制器及其仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TLC5510 IS
PORT( 
      RST    :   IN  STD_LOGIC;
      CLK    :   IN  STD_LOGIC;
      D      :   IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
      CTLOE  :   IN  STD_LOGIC;
      ADCLK  :   OUT STD_LOGIC;
      ADOE   :   OUT STD_LOGIC;
      DATA   :   OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      DCLK   :   OUT STD_LOGIC);
      
END  ENTITY TLC5510;

ARCHITECTURE BEHAVIOURAL OF TLC5510 IS

TYPE ADS_STATES IS (STATE0_TYP,STATE1_TYP);

SIGNAL STA_G_CURRENTSTATE           :  ADS_STATES;
SIGNAL STA_G_NEXTSTATE              :  ADS_STATES;
SIGNAL CTL_GP_LATCHFLAG             :  STD_LOGIC;
SIGNAL CTL_GP_CHIPSELECT            :  STD_LOGIC;

BEGIN

COM:PROCESS(STA_G_CURRENTSTATE)
   BEGIN
      CASE STA_G_CURRENTSTATE IS
       WHEN STATE0_TYP=>ADCLK<='1';CTL_GP_LATCHFLAG<='1';DCLK<='0';
            STA_G_NEXTSTATE<=STATE1_TYP;
       WHEN STATE1_TYP=>ADCLK<='0';CTL_GP_LATCHFLAG<='0';DCLK<='1';
            STA_G_NEXTSTATE<=STATE0_TYP;
       WHEN OTHERS=>ADCLK<='0';CTL_GP_LATCHFLAG<='0';DCLK<='1';
            STA_G_NEXTSTATE<=STATE0_TYP;
END CASE;
END PROCESS COM;
REG:PROCESS(CLK,RST)
    BEGIN 
        IF RST = '0'THEN STA_G_CURRENTSTATE<= STATE0_TYP;
       ELSIF(CLK'EVENT AND CLK ='1')THEN 
          STA_G_CURRENTSTATE<= STA_G_NEXTSTATE;
END IF;
END PROCESS REG;
LATCH:    PROCESS(CTL_GP_LATCHFLAG)
      BEGIN
        IF RST='0'THEN DATA<=(OTHERS=>'0');
        ELSIF CTL_GP_LATCHFLAG 'EVENT AND CTL_GP_LATCHFLAG = '1'THEN DATA<= D;
        END IF;
     END PROCESS LATCH;
CTL_GP_CHIPSELECT<=CTLOE;
ADOE<= NOT CTL_GP_CHIPSELECT;
END ARCHITECTURE BEHAVIOURAL;