📄 pll.fit.rpt
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Fitter report for pll
Mon May 04 10:14:38 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+------------------------------------------+
; Fitter Status ; Failed - Mon May 04 10:14:38 2009 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; pll ;
; Top-level Entity Name ; pll ;
; Family ; Cyclone II ;
; Device ; EP2C8T144C8 ;
; Timing Models ; Final ;
; Total logic elements ; 0 ;
; Total combinational functions ; 0 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 5 / 85 ( 6 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 165,888 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % ) ;
; Total PLLs ; 1 / 2 ( 50 % ) ;
+------------------------------------+------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP2C8T144C8 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
; Use smart compilation ; Off ; Off ;
; Maximum processors allowed for parallel compilation ; 1 ; 1 ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Always Enable Input Buffers ; Off ; Off ;
; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Active Serial ;
; Error detection CRC ; Off ;
; nCEO ; As output driving ground ;
; ASDO,nCSO ; Unreserved ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Mon May 04 10:14:38 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pll -c pll
Info: Selected device EP2C8T144C8 for design "pll"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Error: Can't implement PLL "altpll:altpll_component|pll" as Cyclone II PLL type File: g:/altera/quartus/libraries/megafunctions/altpll.tdf Line: 895
Error: Can't implement clock multiplication and clock division parameter values for PLL "altpll:altpll_component|pll" File: g:/altera/quartus/libraries/megafunctions/altpll.tdf Line: 895
Error: Can't implement PLL because Division and Multiplication cannot be achieved
Warning: Can't achieve requested value multiplication of 5 for clock output altpll:altpll_component|_clk0 of parameter multiplication factor -- achieved value of multiplication of 4
Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:altpll_component|_clk0 port
Info: Implementing clock multiplication of 1, clock division of 4, and phase shift of 0 degrees (0 ps) for altpll:altpll_component|_clk1 port
Error: Quartus II Fitter was unsuccessful. 3 errors, 3 warnings
Info: Allocated 144 megabytes of memory during processing
Error: Processing ended: Mon May 04 10:14:38 2009
Error: Elapsed time: 00:00:00
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