sxh.fit.rpt

TI公司的TLC5510的用VHDL写的控制器及其仿真

Fitter report for SXH
Mon May 04 10:07:55 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. HardCopy II Device Resource Guide
  5. Pin-Out File
  6. Fitter Resource Usage Summary
  7. Input Pins
  8. Output Pins
  9. I/O Bank Usage
 10. All Package Pins
 11. PLL Summary
 12. PLL Usage
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Control Signals
 18. Non-Global High Fan-Out Signals
 19. Interconnect Usage Summary
 20. I/O Rules Summary
 21. I/O Rules Details
 22. I/O Rules Matrix
 23. Fitter Device Options
 24. Operating Settings and Conditions
 25. Advanced Data - General
 26. Advanced Data - Placement Preparation
 27. Advanced Data - Placement
 28. Advanced Data - Routing
 29. Fitter Messages
 30. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Fitter Summary                                                           ;
+-------------------------------+------------------------------------------+
; Fitter Status                 ; Successful - Mon May 04 10:07:55 2009    ;
; Quartus II Version            ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name                 ; SXH                                      ;
; Top-level Entity Name         ; SXH                                      ;
; Family                        ; Stratix II                               ;
; Device                        ; EP2S15F484C3                             ;
; Timing Models                 ; Final                                    ;
; Logic utilization             ; 0 %                                      ;
;     Combinational ALUTs       ; 0 / 12,480 ( 0 % )                       ;
;     Dedicated logic registers ; 0 / 12,480 ( 0 % )                       ;
; Total registers               ; 0                                        ;
; Total pins                    ; 6 / 343 ( 2 % )                          ;
; Total virtual pins            ; 0                                        ;
; Total block memory bits       ; 0 / 419,328 ( 0 % )                      ;
; DSP block 9-bit elements      ; 0 / 96 ( 0 % )                           ;
; Total PLLs                    ; 1 / 6 ( 17 % )                           ;
; Total DLLs                    ; 0 / 2 ( 0 % )                            ;
+-------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; AUTO                           ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;