tlc5510.tan.summary

TI公司的TLC5510的用VHDL写的控制器及其仿真

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.402 ns
From           : D[0]
To             : DATA[0]~reg0
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.197 ns
From           : DATA[2]~reg0
To             : DATA[2]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.532 ns
From           : CTLOE
To             : ADOE
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.490 ns
From           : D[7]
To             : DATA[7]~reg0
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 360.10 MHz ( period = 2.777 ns )
From           : STA_G_CURRENTSTATE
To             : STA_G_CURRENTSTATE
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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