tb_infifo_rev0.1.v

Verilog jpec coder encoder source code

//////////////////////////////////////////////
//	
//	Module Name:	tb_infifo
//	Description:	Testbench for input fifo.
//	Author:			James Rosenthal
//	Date:			10/28/04
//
//
//	Version	Date		Modifications
//	---------------------------------
//	0.0		10/28/04	Initial
//	0.1		11/20/04	Fit New Design
//						Redesigned tests
//						Test for flags
//						Test for Error Flags
//						
//	///////////////////////////////////////////

`timescale 1ns / 10ps

module tb_infifo();

	reg sysclk, extclk;
	reg wr_en, rd_en, rst;
	reg [12:0] din;
	
	wire [12:0] dout;
	wire full, empty, error;

	integer i;
	reg [12:0] in [255:0];

	// Instantiate Module
	input_fifo infifo(
		.sysclk(sysclk),
		.extclk(extclk),
		.rd_en(rd_en),
		.wr_en(wr_en),
		.din(din),
		.dout(dout),
		.full(full),
		.empty(empty),
		.rst(rst),
		.error(error)
	);

	always #5 sysclk <= ~sysclk;

	initial
	begin
		in[0] <= 13'h1fff;
		for(i=1; i<256; i=i+1)
			in[i] <= i;
	end
	
	always @ (posedge sysclk)
	begin
		if(error)
		begin
			$display("ERROR In FIFO State Machine");
			break;
		end
	end
	
	initial
	begin
		#0 extclk <= 1'b0;
		#0 syclk <= 1'b0;
		#0 rst <= 1'b0;
		#0 din <= 13'h0;
		#0 wr_en <= 1'b0;
		#0 rd_en <= 1'b0;

		#20 rst <= 1'b1;

		test_reset;
		
		test_status; // Test Empty & Full Flags
		test_error;
		
	end
	
	task test_reset;
	begin
		@(posedge clk);
		rst <= 1'b0;
		repeat(5)@(posedge clk);
		rst <= 1'b1;
		repeat(5)@(posedge clk);
		if(!empty || full)
		begin
			$display("ERROR: Reset Unsuccessful");
			$stop;
		end
	end
	endtask

	task check_full;
	begin
		if(!full) $display("ERROR: FIFO Not Full");
		if(empty) $display("ERROR: FIFO Empty");
	end
	endtask

	task check_empty;
	begin
		if(full) $display("ERROR: FIFO is Full");
		if(!empty) $display("ERROR: FIFO is not Empty");
	end
	endtask
	
	task check_noflag;
	begin
		if(full) $display("ERROR: FIFO is Full");
		if(empty) $display("ERROR: FIFO is Empty");
	end
	endtask

	task test_full;
	begin
		// FIFO Reset
		repeat(10)@(posedge clk);
		test_reset;

		// Write 255 Values, Check Full
		write_255;

		// Read 255 Values, Verify Reads
		read_255;

		// Adjust Address Pointers (Write 20, Read 20)
		repeat(5)@(posedge clk);
		for(i=10; i<30; i=i+1)
		begin
			@(posedge clk);
			extclk <= 1'b1;
			wr_en <= 1'b1
			din <= in[i];
			@(posedge clk);
			extclk <= 1'b0;
			wr_en <= 1'b0;
			repeat(2)@(posedge clk);
		end

		check_noflag;
		
		for(i=10; i<30; i=i+1)
		begin
			@(posedge clk);
			extclk <= 1'b1;
			rd_en <= 1'b1;
			@(posedge clk);
			extclk <= 1'b0;
			rd_en <= 1'b0;
			if(dout != in[i+10])
				$display("ERROR: Expected: %x, Recieved: %x",in[i],dout);
			@(posedge clk);
		end

		check_empty;
		
		// Write 255 Values, Check Full
		write_255;

		// Read 255 Values, Verify Reads
		read_255;
		
		// FIFO Reset
		test_reset;
		
	end
	endtask

	task write_255;
	begin
		repeat(5)@(posedge clk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge clk);
			ext_clk <= 1'b1;
			wr_en <= 1'b1;
			din <= in[i];
			@(posedge clk);
			extclk <= 1'b0;
			wr_en <= 1'b0;
			repeat(2)@(posedge clk);
		end

		check_full;
	end
	endtask

	task read_255;
	begin
		repeat(5)@(posedge clk);
		for(i=0; i<255; i=i+1);
		begin
			@(posedge clk);
			extclk <= 1'b1;
			rd_en <= 1'b1;
			@(posedge clk);
			extclk <= 1'b0;
			rd_en <= 1'b0;
			if(dout != in[i]) 
				$display("ERROR: Expected: %x, Recieved: %x",in[i],dout);
			@(posedge clk);
		end
		
		check_empty;	
	end
	endtask

	task test_error;
	begin
		// Reset FIFO
		repeat(10)@(posedge clk);
		test_reset;

		// Write 256 Values
		write_255;
		@(posedge clk);
		extclk <= 1'b1;
		wr_en <= 1'b1;
		din <= 13'h1fff;
		@(posedge clk);
		extclk <= 1'b0;
		wr_en <= 1'b0;
		din <= 13'h0;
		@(negedge clk);
		if(!error) 
			$display("ERROR: Write on Full did not raise error flag");

		// Reset FIFO
		repeat(10)@(posedege clk);
		test_reset;

		// Read On Empty
		@(posedge clk);
		extclk <= 1'b1;
		rd_en <= 1'b1;
		@(posedge clk);
		extclk <= 1'b0;
		rd_en <= 1'b0;
		@(negedge clk);
		if(!error)
			$display("ERROR: Read On Empty did not raise error flag");

	end
	endtask
	
endmodule