tb_infifo_rev0.2.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////
//	
//	Module Name:	tb_infifo
//	Description:	Testbench for input fifo.
//	Author:			James Rosenthal
//	Date:			10/28/04
//
//
//	Notes:
//	
//	4 Cycle Cases to Test:
//	----------------------
//	- Different Clock Cycle Cases to Test.
//	- Assume DSP Cycle starts on first posedge
//	DSP Cycle |--__--__--__--__--__--__--__--__
//	FPGA (1)  |----------------________________
//	FPGA (2)  |__----------------______________
//	FPGA (3)  |____----------------____________
//	FPGA (4)  |______----------------__________
//
//	
//	Version	Date		Modifications
//	---------------------------------
//	0.0		10/28/04	Initial
//	0.1		11/20/04	Fit New Design
//						Redesigned tests
//						Test for flags
//						Test for Error Flags
//	0.2		11/29/04	Remove extclk and wr_en
//						Add nce, awe
//						Test four clock cycle cases
//						
//						
//		
////////////////////////////////////////////////////

`timescale 1ns / 10ps

module tb_infifo();

	reg sysclk;
	reg nce, awe, rd_en, rst;
	reg [12:0] din;
	
	wire [12:0] dout;
	wire full, empty, error;

	integer i, expected, recieved;
	reg [12:0] exp;
	reg [12:0] in [255:0];

	// Instantiate Module
	input_fifo infifo(
		.sysclk(sysclk),
		.awe(awe),
		.nce(nce),
		.rd_en(rd_en),		
		.din(din),
		.dout(dout),
		.full(full),
		.empty(empty),
		.rst(rst),
		.error(error)
	);

	always #5 sysclk <= ~sysclk;

	initial
	begin
		in[0] <= 13'h1fff;
		for(i=1; i<256; i=i+1)
			in[i] <= i;
	end
	
	always @ (posedge sysclk)
	begin
		if(error)
		begin
			$display("%t: ERROR In FIFO State Machine", $time);
		end
	end
	
	initial
	begin
		#0 sysclk <= 1'b0;
		#0 rst <= 1'b0;
		#0 din <= 13'h0;
		#0 rd_en <= 1'b0;
		#0 awe <= 1'b1;
		#0 nce <= 1'b1;
		
		#20 rst <= 1'b1;

		test_reset;
		test_full;
		test_error;
		
	end
	
	task test_reset;
	begin
		@(posedge sysclk);
		rst <= 1'b0;
		repeat(5)@(posedge sysclk);
		rst <= 1'b1;
		repeat(5)@(posedge sysclk);
		if(!empty || full)
		begin
			$display("%t: ERROR: Reset Unsuccessful",$time);
			$stop;
		end
	end
	endtask

	task check_full;
	begin
		if(!full) $display("%t: ERROR: FIFO Not Full",$time);
		if(empty) $display("%t: ERROR: FIFO Empty", $time);
	end
	endtask

	task check_empty;
	begin
		if(full) $display("%t: ERROR: FIFO is Full", $time);
		if(!empty) $display("%t: ERROR: FIFO is not Empty", $time);
	end
	endtask
	
	task check_noflag;
	begin
		if(full) $display("%t: ERROR: FIFO is Full", $time);
		if(empty) $display("%t: ERROR: FIFO is Empty", $time);
	end
	endtask

	task test_full;
	begin
		// FIFO Reset
		repeat(10)@(posedge sysclk);
		test_reset;

		// Write 255 Values, Check Full
		write_255;

		// Read 255 Values, Verify Reads
		read_255;

		// Adjust Address Pointers (Write 20, Read 20)
		repeat(5)@(posedge sysclk);
		for(i=10; i<30; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			repeat(3)@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
			repeat(2)@(posedge sysclk);
		end

		check_noflag;
		
		for(i=10; i<30; i=i+1)
		begin
			@(posedge sysclk);
			rd_en <= 1'b1;
			@(posedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved)
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			@(posedge sysclk);
		end

		check_empty;
		
		// Write 255 Values, Check Full
		write_255;

		// Read 255 Values, Verify Reads
		read_255;
		
		// FIFO Reset
		test_reset;
		
	end
	endtask

	task write_255;
	begin
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			repeat(3)@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end

		check_full;
	end
	endtask

	task read_255;
	begin
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			rd_en <= 1'b1;
			@(posedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved) 
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			@(posedge sysclk);
		end
		
		check_empty;	
	end
	endtask

	task test_error;
	begin
		// Reset FIFO
		repeat(10)@(posedge sysclk);
		test_reset;

		// Write 256 Values
		write_255;
		@(posedge sysclk);
		$display("ERROR SHOULD OCCUR HERE");
		nce <= 1'b0;
		#2 awe <= 1'b0;
		#1 din <= 13'h1ABC;
		repeat(3) @(posedge sysclk);
		nce <= 1'b1;
		awe <= 1'b1;
//		if(!error) 
//			$display("%t: ERROR: Write on Full did not raise error flag", $time);

		// Read one value to check if write was successful
		repeat(5)@(posedge sysclk);
		rd_en <= 1'b1;
		@(posedge sysclk);
		rd_en <= 1'b0;
		@(negedge sysclk);
		if(dout == 13'h1ABC)
			$display("%t: ERROR: Write on Full was Successful",$time);

		// Reset FIFO
		repeat(10)@(posedge sysclk);
		test_reset;

		// Read On Empty - An error would require read_sm for this fifo. 
		@(posedge sysclk);
		rd_en <= 1'b1;
		@(posedge sysclk);
		rd_en <= 1'b0;
		@(negedge sysclk);
		if(!error)
			$display("%t: ERROR: Read On Empty did not raise error flag",$time);

	end
	endtask
	
endmodule