tb_infifo_rev0.3.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////
//	
//	Module Name:	tb_infifo
//	Description:	Testbench for input fifo.
//	Author:			James Rosenthal
//	Date:			10/28/04
//
//
//	Version	Date		Modifications
//	---------------------------------
//	0.0		10/28/04	Initial
//	0.1		11/20/04	Fit New Design
//						Redesigned tests
//						Test for flags
//						Test for Error Flags
//	0.2		11/29/04	Remove extclk and wr_en
//						Add nce, awe
//						Test four clock cycle cases
//	0.3		11/30/04	Add extclk to control DSP 
//						signals.  sysclk is derived 
//						from extclk						
//		
////////////////////////////////////////////////////

`timescale 1ns / 10ps

module tb_infifo();

	//
	// Registers to simulate Inputs to input fifo
	//
	
	reg extclk;		// DSP clock (100 MHz)
	reg nce;		// Active low chip enable
	reg awe;		// Asynchronous Write Enable
	reg rd_en;		// Read Enable from FPGA
	reg rst;		// Async. Active Low Reset
	reg [1:0] clkselect; // Mux select for clock

	reg [ 4:0] clkdiv;	
	reg [12:0] din;
	
	wire sysclk;
	
	//
	// Wires to capture outputs of input FIFO
	//
	
	wire [12:0] dout;
	
	wire full;		// FIFO Full Flag
	wire empty;		// FIFO Empty Flag
	wire error;		// Error flag (for testing only)
	

	//
	// Variables
	// 
	
	integer i;			// index variable
    integer	expected;	// expected value from read
	integer recieved;	// value recieved from read

	reg [12:0] exp;		// 13-bit expected value
	reg [12:0] in [255:0]; // input list

	reg [1:0] test;	// 4 tests to define cycle test

	//
	// Instantiate DUT
	// 
	
	input_fifo dut(
		.sysclk(sysclk),
		.awe(awe),
		.nce(nce),
		.rd_en(rd_en),		
		.din(din),
		.dout(dout),
		.full(full),
		.empty(empty),
		.rst(rst),
		.error(error)
	);

	// 100 MHz Clock - 10ns Period
	always #5 extclk = ~extclk;

	// Derive sysclk
	always @ (posedge extclk or negedge rst)
	begin
		if(!rst)
			clkdiv <= 5'h0;
		else 
			clkdiv <= clkdiv + 1;
	end
	
	// clkdiv[0] is used to test fpga cycles starting at different times
	assign sysclk = clkselect == 2'h00 ? clkdiv[1] : // 25 MHz - 40ns Period
					clkselect == 2'h01 ? clkdiv[2] : // 12.5 MHz - 80ns Period
					clkselect == 2'h10 ? clkdiv[3] : // 6.25 MHz - 160ns Period
					clkdiv[4];	// 3.125 MHz - 320ns Period
	
	// Initialize Input List
	initial
	begin
		in[0] <= 13'h1fff;
		for(i=1; i<256; i=i+1)
			in[i] <= i;
	end
	
	// Testbench Start
	initial
	begin
		#0 clkselect <= 2'h0;
		#0 extclk <= 1'b0;
		#0 rst <= 1'b0;
		#0 din <= 13'h0;
		#0 rd_en <= 1'b0;
		#0 awe <= 1'b1;
		#0 nce <= 1'b1;
		
		#20 rst <= 1'b1;

		test_reset;
		test_rw1;
		test_error;


		// test dsp cycle start on posedge sysclk (pe,s0)
		// test dsp cycle start on first negedge of sysclk (pe,s1)
		// test dsp cycle start on second posedge sysclk
		
	end
	
	task test_rw1;
	// This task will test reads/writes the fifo while checking that the 
	// flags are set and unset correctly.  The dsp read and write cycles
	// will start on a positive edge of the sysclk as well as extclk
	begin
		$display("##### %t: Test Reads and Writes to FIFO #####",$time);
		repeat(10)@(posedge sysclk);
		
		// FIFO Reset
		test_reset;

		// Write 255 Values, Check Full
		write_255;

		// Read 255 Values, Verify Reads, Check Empty
		read_255;

		// Adjust Address Pointers (Write 20, Read 20)
		adjust_ptr;
		
		// Write 255 Values, Check Full
		write_255;

		// Read 255 Values, Verify Reads
		read_255;
		
		// FIFO Reset
		test_reset;
		
	end
	endtask

	task test_reset;
	// This task will test the reset functionality
	begin
		$display("##### %t: Test Reset #####",$time);
		
		@(posedge sysclk);
		rst <= 1'b0;
		repeat(5)@(posedge sysclk);
		rst <= 1'b1;
		repeat(5)@(posedge sysclk);
		if(!empty || full)
		begin
			$display("%t: ERROR: Reset Unsuccessful",$time);
			$stop;
		end
		else
			$display("***** %t: Reset was Successful *****",$time);
	end
	endtask

	task check_full;
	// This task will verify that the FIFO is full
	begin
		if(!full) $display("%t: ERROR: FIFO Not Full",$time);
		if(empty) $display("%t: ERROR: FIFO Empty", $time);
	end
	endtask

	task check_empty;
	// This task will verify that the FIFO is empty
	begin
		if(full) $display("%t: ERROR: FIFO is Full", $time);
		if(!empty) $display("%t: ERROR: FIFO is not Empty", $time);
	end
	endtask
	
	task check_noflag;
	// This task will verify that no flags are set
	begin
		if(full) $display("%t: ERROR: FIFO is Full", $time);
		if(empty) $display("%t: ERROR: FIFO is Empty", $time);
	end
	endtask

	task adjust_ptr;
	// This task will adjust set that read and write pointers 
	// to location 19, with the FIFO empty
	begin
		repeat(5)@(posedge sysclk);

		// Write 20 values
		for(i=70; i<90; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			repeat(3)@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
			@(posedge clk);
		end

		// Verify no flags are set
		check_noflag;

		// Read 20 Values
		for(i=70; i<90; i=i+1)
		begin
			@(posedge sysclk);
			rd_en <= 1'b1;
			@(posedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved)
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			@(posedge sysclk);
		end

		// Verify FIFO is empty
		check_empty;
	endtask
	

	task write_255;
	begin
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			repeat(3)@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end

		check_full;
	end
	endtask

	task read_255;
	begin
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			rd_en <= 1'b1;
			@(posedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved) 
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			@(posedge sysclk);
		end
		
		check_empty;	
	end
	endtask

	task test_error;
	begin
		// Reset FIFO
		repeat(10)@(posedge sysclk);
		test_reset;

		// Write 256 Values
		write_255;
		@(posedge sysclk);
		$display("ERROR SHOULD OCCUR HERE");
		nce <= 1'b0;
		#2 awe <= 1'b0;
		#1 din <= 13'h1ABC;
		repeat(3) @(posedge sysclk);
		nce <= 1'b1;
		awe <= 1'b1;
//		if(!error) 
//			$display("%t: ERROR: Write on Full did not raise error flag", $time);

		// Read one value to check if write was successful
		repeat(5)@(posedge sysclk);
		rd_en <= 1'b1;
		@(posedge sysclk);
		rd_en <= 1'b0;
		@(negedge sysclk);
		if(dout == 13'h1ABC)
			$display("%t: ERROR: Write on Full was Successful",$time);

		// Reset FIFO
		repeat(10)@(posedge sysclk);
		test_reset;

		// Read On Empty - An error would require read_sm for this fifo. 
		@(posedge sysclk);
		rd_en <= 1'b1;
		@(posedge sysclk);
		rd_en <= 1'b0;
		@(negedge sysclk);
		if(!error)
			$display("%t: ERROR: Read On Empty did not raise error flag",$time);

	end
	endtask
	
endmodule