📄 tb_outfifo_rev0.0.v
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////////////////////////////////////////////////////
//
// Module Name: tb_outfifo
// Description: Testbench for output fifo.
// Author: James Rosenthal
// Date: 12/06/04
//
// Version Date Modifications
// ---------------------------------
// 0.0 12/06/04 - Initial
//
////////////////////////////////////////////////////
`timescale 1ns / 10ps
module tb_outfifo();
//
// Parameters
//
parameter verbose = 1;
//
// Registers to Simulate Inputs
//
reg sysclk; // FPGA System Clock
reg rst; // Async. Active Low Reset
reg are; // Async. Read Enable
reg nce; // Active Low Chip Enable
reg wr_en; // Write Enable
reg [12:0] din; // Data Input
//
// Wires to Capture Output
//
wire [12:0] dout; // Data Output
wire full, empty; // FIFO Status Flags
wire error; // Read On Empty Error
//
// Other Variables
//
integer i; // indexing variable
integer expected; // Expected Value
integer recieved; // Recieved Value
integer numerr; // Number of errors
reg [12:0] exp; // Expected value (13-bit)
reg [12:0] in [255:0]; // Input List
//
// Instantiate DUT
//
output_fifo dut(
.sysclk(sysclk),
.rst(rst),
.are(are),
.nce(nce),
.wr_en(wr_en),
.din(din),
.dout(dout),
.full(full),
.empty(empty),
.error(error)
);
// Create 25 MHz FPGA clock
always #20 sysclk = ~sysclk;
// Initialize Input List
initial
begin
in[0] <= 13'h1fff;
for(i=1; i<256; i=i+1)
in[i] <= i;
end
// Testbench Start
initial
begin
#0 sysclk <= 1'b0;
#0 rst <= 1'b0;
#0 din <= 13'h0;
#0 wr_en <= 1'b0;
#0 are <= 1'b1;
#0 nce <= 1'b1;
#20 rst <= 1'b1;
test_reset;
test_rw1;
test_rw2;
test_error;
$stop;
end
task test_reset;
// This task will test the reset functionality
begin
$display("%t: Test Reset",$time);
repeat(5)@(posedge sysclk);
rst <= 1'b0;
repeat(5)@(posedge sysclk);
rst <= 1'b1;
if(!empty || full)
begin
$display("%t: ERROR: Reset Unsuccessful",$time);
$stop;
end
repeat(5)@(posedge sysclk);
$display("%t: Reset Successful",$time);
end
endtask
task test_rw1;
// This task will test reads and writes to the FIFO,
// while verifying the flags, and that reads and writes
// complete successfully. The DSP read cycle is synchronous
// with the positive edge of the sysclk.
begin
$display("##### %t: Test RW 1 #####",$time);
// Reset FIFO
test_reset;
// Write 256 Values to FIFO, Check Full
// Only 255 in FIFO, but read state machine
// will read one value out into temp space.
if(verbose) $display("%t: Write 256 Values to FIFO",$time);
for(i=0; i<256; i=i+1)
begin
@(posedge sysclk);
wr_en <= 1'b1;
din <= in[i];
@(posedge sysclk);
wr_en <= 1'b0;
end
@(posedge sysclk);
if(verbose) $display("%t: Finished Writing, Check Full",$time);
check_full;
// Read 256 Values from FIFO, Verify, Check Empty
if(verbose) $display("%t: Read/Verify 256 Values from FIFO",$time);
numerr = 0;
for(i=0; i<256; i=i+1)
begin
exp <= in[i];
@(posedge sysclk);
nce <= 1'b0;
#2 are <= 1'b0;
@(posedge sysclk);
nce <= 1'b1;
are <= 1'b1;
expected = {{19{exp[12]}},exp};
recieved = {{19{dout[12]}},dout};
if(expected != recieved)
begin
numerr = numerr + 1;
$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
$stop;
end
end
if(verbose && !numerr)
$display("%t: Read/Verify 256 Values Successfully, Check Empty",$time);
check_empty;
// Adjust address Pointers
$display("%t: Adjust Address Pointers",$time);
// Write 20 Values to FIFO, Check No Flags Set
if(verbose) $display("%t: Write 20 Values to FIFO",$time);
for(i=20; i<40; i=i+1)
begin
@(posedge sysclk);
wr_en <= 1'b1;
din <= in[i];
@(posedge sysclk);
wr_en <= 1'b0;
end
if(verbose) $display("%t: Finished Writing, Check No Flags",$time);
check_noflag;
// Read 20 Values from FIFO, Verify, Check Empty
if(verbose) $display("%t: Read/Verify 20 Values from FIFO",$time);
numerr = 0;
for(i=20; i<40; i=i+1)
begin
exp <= in[i];
@(posedge sysclk);
nce <= 1'b0;
#2 are <= 1'b0;
@(posedge sysclk);
nce <= 1'b1;
are <= 1'b1;
expected = {{19{exp[12]}},exp};
recieved = {{19{dout[12]}},dout};
if(expected != recieved)
begin
numerr = numerr + 1;
$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
$stop;
end
end
if(verbose && !numerr)
$display("%t: Read/Verify 20 Values Successfully, Check Empty",$time);
check_empty;
// Write 256 Values to FIFO, Check Full
if(verbose) $display("%t: Write 256 Values to FIFO",$time);
for(i=0; i<256; i=i+1)
begin
@(posedge sysclk);
wr_en <= 1'b1;
din <= in[i];
@(posedge sysclk);
wr_en <= 1'b0;
end
@(posedge sysclk);
if(verbose) $display("%t: Finished Writing, Check Full",$time);
check_full;
// Read 256 Values from FIFO, Verify, Check Empty
if(verbose) $display("%t: Read/Verify 256 Values from FIFO",$time);
numerr = 0;
for(i=0; i<256; i=i+1)
begin
exp <= in[i];
@(posedge sysclk);
nce <= 1'b0;
#2 are <= 1'b0;
@(posedge sysclk);
nce <= 1'b1;
are <= 1'b1;
expected = {{19{exp[12]}},exp};
recieved = {{19{dout[12]}},dout};
if(expected != recieved)
begin
numerr = numerr + 1;
$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
$stop;
end
end
if(verbose && !numerr)
$display("%t: Read/Verify 256 Values Successfully, Check Empty",$time);
check_empty;
// Reset FIFO
test_reset;
$display("##### %t: End Test RW 1 #####",$time);
end
endtask
task test_rw2;
// This task will test reads and writes to the FIFO,
// while verifying the flags, and that reads and writes
// complete successfully. The DSP read cycle is synchronous
// with the negative edge of the sysclk.
begin
$display("##### %t: Test RW 2 #####",$time);
// Reset FIFO
test_reset;
// Write 256 Values to FIFO, Check Full
if(verbose) $display("%t: Write 256 Values to FIFO",$time);
for(i=0; i<256; i=i+1)
begin
@(negedge sysclk);
wr_en <= 1'b1;
din <= in[i];
@(negedge sysclk);
wr_en <= 1'b0;
end
if(verbose) $display("%t: Finished Writing, Check Full",$time);
check_full;
// Read 256 Values from FIFO, Verify, Check Empty
if(verbose) $display("%t: Read/Verify 256 Values from FIFO",$time);
numerr = 0;
for(i=0; i<256; i=i+1)
begin
exp <= in[i];
@(negedge sysclk);
nce <= 1'b0;
#2 are <= 1'b0;
@(negedge sysclk);
#5
nce <= 1'b1;
are <= 1'b1;
expected = {{19{exp[12]}},exp};
recieved = {{19{dout[12]}},dout};
if(expected != recieved)
begin
numerr = numerr + 1;
$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
$stop;
end
end
if(verbose && !numerr)
$display("%t: Read/Verify 256 Values Successfully, Check Empty",$time);
check_empty;
// Adjust address Pointers
$display("%t: Adjust Address Pointers",$time);
// Write 20 Values to FIFO, Check No Flags Set
if(verbose) $display("%t: Write 20 Values to FIFO",$time);
for(i=20; i<40; i=i+1)
begin
@(negedge sysclk);
wr_en <= 1'b1;
din <= in[i];
@(negedge sysclk);
wr_en <= 1'b0;
end
if(verbose) $display("%t: Finished Writing, Check No Flags",$time);
check_noflag;
// Read 20 Values from FIFO, Verify, Check Empty
if(verbose) $display("%t: Read/Verify 20 Values from FIFO",$time);
numerr = 0;
for(i=20; i<40; i=i+1)
begin
exp <= in[i];
@(negedge sysclk);
nce <= 1'b0;
#2 are <= 1'b0;
@(negedge sysclk);
#5
nce <= 1'b1;
are <= 1'b1;
expected = {{19{exp[12]}},exp};
recieved = {{19{dout[12]}},dout};
if(expected != recieved)
begin
numerr = numerr + 1;
$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
$stop;
end
end
if(verbose && !numerr)
$display("%t: Read/Verify 20 Values Successfully, Check Empty",$time);
check_empty;
// Write 256 Values to FIFO, Check Full
if(verbose) $display("%t: Write 256 Values to FIFO",$time);
for(i=0; i<256; i=i+1)
begin
@(negedge sysclk);
wr_en <= 1'b1;
din <= in[i];
@(negedge sysclk);
wr_en <= 1'b0;
end
if(verbose) $display("%t: Finished Writing, Check Full",$time);
check_full;
// Read 256 Values from FIFO, Verify, Check Empty
if(verbose) $display("%t: Read/Verify 256 Values from FIFO",$time);
numerr = 0;
for(i=0; i<256; i=i+1)
begin
exp <= in[i];
@(negedge sysclk);
nce <= 1'b0;
#2 are <= 1'b0;
@(negedge sysclk);
#5
nce <= 1'b1;
are <= 1'b1;
expected = {{19{exp[12]}},exp};
recieved = {{19{dout[12]}},dout};
if(expected != recieved)
begin
numerr = numerr + 1;
$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
$stop;
end
end
if(verbose && !numerr)
$display("%t: Read/Verify 255 Values Successfully, Check Empty",$time);
check_empty;
// Reset FIFO
test_reset;
$display("##### %t: End Test RW 2 #####",$time);
end
endtask
task test_error;
// This will test to see that a read on empty error flag occurs.
begin
$display("##### %t: Test Error Flag #####",$time);
test_reset;
// Read on Empty
if(verbose) $display("%t: Attempt to Read on empty",$time);
@(posedge sysclk);
nce <= 1'b0;
#2 are <= 1'b0;
@(negedge sysclk);
if(!error)
begin
$display("%t: ERROR: Error flag no raised on read on empty",$time);
$stop;
end
@(posedge sysclk);
nce <= 1'b1;
are <= 1'b1;
$display("##### %t: Error Test completed Successfully",$time);
end
endtask
task check_full;
// This task Verifies the Full flag is set
begin
if(empty)
begin
$display("%t: ERROR FIFO Reads Empty",$time);
$stop;
end
if(!full)
begin
$display("%t: ERROR FIFO Does not Read Full",$time);
$stop;
end
if(!empty && full) $display("%t: FIFO Is Full",$time);
end
endtask
task check_empty;
// This task will verify that the FIFO empty flag is set
begin
if(!empty)
begin
$display("%t: ERROR FIFO is Not empty",$time);
$stop;
end
if(full)
begin
$display("%t: ERROR FIFO is Full",$time);
$stop;
end
if(empty && !full) $display("%t: FIFO is empty",$time);
end
endtask
task check_noflag;
// This task verifies no flags are set.
begin
if(empty)
begin
$display("%t: ERROR FIFO is Empty",$time);
$stop;
end
if(full)
begin
$display("%t: ERROR FIFO is Full",$time);
$stop;
end
if(!empty && !full) $display("%t: No Flags are set",$time);
end
endtask
endmodule
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