📄 tb_infifo_rev0.4.v

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////////////////////////////////////////////////////
//	
//	Module Name:	tb_infifo
//	Description:	Testbench for input fifo.
//	Author:			James Rosenthal
//	Date:			10/28/04
//
//
//	Version	Date		Modifications
//	---------------------------------
//	0.0		10/28/04	- Initial
//	0.1		11/20/04	- Fit New Design
//						- Redesigned tests
//						- Test for flags
//						- Test for Error Flags
//	0.2		11/29/04	- Remove extclk and wr_en
//						- Add nce, awe
//						- Test four clock cycle cases
//	0.3		11/30/04	- Add extclk to control DSP 
//						  signals.  sysclk is derived 
//						  from extclk						
//	0.4		12/04/04	- Remove write_255 and read_255
//						  These tasks are now part of 
//						  individual tests rw1,2,3, and 4
//						  which test the dsp write cycles
//						  occuring at different moments 
//						  with respect to the sysclk
//						- Remove extclk as it is not 
//						  used in any place.
//						- Have sysclk only and create
//						  DSP cycles based on it.
//								
////////////////////////////////////////////////////

`timescale 1ns / 10ps

module tb_infifo();

	//
	// Registers to simulate Inputs to input fifo
	//
	
	reg nce;		// Active low chip enable
	reg awe;		// Asynchronous Write Enable
	reg rd_en;		// Read Enable from FPGA
	reg rst;		// Async. Active Low Reset

	reg [12:0] din;
	
	reg sysclk;		// FPGA clock
	
	//
	// Wires to capture outputs of input FIFO
	//
	
	wire [12:0] dout;
	
	wire full;		// FIFO Full Flag
	wire empty;		// FIFO Empty Flag
	wire error;		// Error flag (for testing only)
	

	//
	// Variables
	// 
	
	integer i;			// index variable
	integer num_errors;	// # of Errors 
    integer	expected;	// expected value from read
	integer recieved;	// value recieved from read

	reg [12:0] exp;		// 13-bit expected value
	reg [12:0] in [255:0]; // input list

	//
	// Instantiate DUT
	// 
	
	input_fifo dut(
		.sysclk(sysclk),
		.awe(awe),
		.nce(nce),
		.rd_en(rd_en),		
		.din(din),
		.dout(dout),
		.full(full),
		.empty(empty),
		.rst(rst),
		.error(error)
	);

	// Create 25 MHz FPGA clock
	always #20 sysclk = ~sysclk;

	// Initialize Input List
	initial
	begin
		in[0] <= 13'h1fff;
		for(i=1; i<256; i=i+1)
			in[i] <= i;
	end
	
	// Testbench Start
	initial
	begin
		#0 sysclk <= 1'b0;
		#0 rst <= 1'b0;
		#0 din <= 13'h0;
		#0 rd_en <= 1'b0;
		#0 awe <= 1'b1;
		#0 nce <= 1'b1;
		
		#20 rst <= 1'b1;

		test_reset;
		test_rw1;
		test_rw2;
		test_error;
		$stop;

	end
	
	task test_rw1;
	// This task will test reads/writes the fifo while checking that the 
	// flags are set and unset correctly.  The DSP cycle starts at posedge 
	// of FPGA clock.
	begin
		
		$display("##### %t: Test Reads and Writes to FIFO 1 #####",$time);
		repeat(10)@(posedge sysclk);
		
		// FIFO Reset
		test_reset;

		// Write 255 Values, Check Full
		$display("%t: Write 255 Values",$time);
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end
		$display("%t: Finish 255 Writes, Check Full",$time);

		check_full;

		// Read 255 Values, Verify Reads, Check Empty
		$display("%t: Read/Verify 255 Values",$time);
		num_errors = 0;
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			rd_en <= 1'b1;
			@(posedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved) 
			begin
				num_errors = num_errors + 1;
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			end
		end
		if(num_errors == 0) $display("%t: Read/Verified 255 Values Successfullly, Check Empty",$time);
		
		check_empty;

		// Adjust Address Pointers (Write 20, Read 20)
		
		$display("%t: Adjust Address Pointers",$time);
		
		repeat(5)@(posedge sysclk);

		// Write 20 values
		$display("%t: Write 20 Values to FIFO",$time);
		for(i=70; i<90; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end
		
		$display("%t: Finished Writing 20 Values, Check no flags are set",$time);
		
		// Verify no flags are set
		check_noflag;

		// Read 20 Values
		$display("%t: Read/Verify 20 Values from FIFO",$time);
		num_errors = 0;
		for(i=70; i<90; i=i+1)
		begin
			@(posedge sysclk);
			rd_en <= 1'b1;
			@(posedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved)
			begin
				num_errors = num_errors + 1;
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			end
		end
		if(num_errors == 0) $display("%t: Read/Verified 255 Values Successfullly, Check Empty",$time);
	
		// Verify FIFO is empty
		check_empty;
		
		// Write 255 Values, Check Full
		$display("%t: Write 255 Values",$time);
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end
		$display("%t: Write 255 Values Complete, Check Full",$time);
		check_full;

		// Read 255 Values, Verify Reads
		$display("%t: Read/Verify 255 Values",$time);
		num_errors = 0;
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			rd_en <= 1'b1;
			@(posedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved) 
			begin
				num_errors = num_errors + 1;
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			end
		end
		if(num_errors == 0) $display("%t: Read/Verified 255 Values Successfullly, Check Empty",$time);
		check_empty;	
		
		// FIFO Reset
		test_reset;

		$display("##### %t: End Task test_rw1 #####",$time);
		
	end
	endtask //end task test_rw1

	task test_rw2;
	// This task will test reads/writes the fifo while checking that the 
	// flags are set and unset correctly.  The dsp read and write cycles
	// will start on a negative edge of the sysclk.
	begin
		
		$display("##### %t: Test Reads and Writes to FIFO 2 #####",$time);
		repeat(10)@(posedge sysclk);
		
		// FIFO Reset
		test_reset;

		// Write 255 Values, Check Full
		$display("%t: Write 255 Values",$time);
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(negedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			@(negedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end
		$display("%t: Finish 255 Writes, Check Full",$time);
		@(negedge sysclk);
		check_full;

		// Read 255 Values, Verify Reads, Check Empty
		$display("%t: Read/Verify 255 Values",$time);
		num_errors = 0;
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(negedge sysclk);
			rd_en <= 1'b1;
			@(negedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			@(posedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved) 
			begin
				num_errors = num_errors + 1;
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			end
		end
		if(num_errors == 0) $display("%t: Read/Verified 255 Values Successfullly, Check Empty",$time);
		
		check_empty;

		// Adjust Address Pointers (Write 20, Read 20)
		
		$display("%t: Adjust Address Pointers",$time);
		
		repeat(5)@(posedge sysclk);

		// Write 20 values
		$display("%t: Write 20 Values to FIFO",$time);
		for(i=70; i<90; i=i+1)
		begin
			@(negedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			@(negedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end
		
		$display("%t: Finished Writing 20 Values, Check no flags are set",$time);
		
		// Verify no flags are set
		check_noflag;

		// Read 20 Values
		$display("%t: Read/Verify 20 Values from FIFO",$time);
		num_errors = 0;
		for(i=70; i<90; i=i+1)
		begin
			@(negedge sysclk);
			rd_en <= 1'b1;
			@(negedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			@(posedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved)
			begin
				num_errors = num_errors + 1;
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			end
		end
		if(num_errors == 0) $display("%t: Read/Verified 255 Values Successfullly, Check Empty",$time);
	
		// Verify FIFO is empty
		check_empty;
		
		// Write 255 Values, Check Full
		$display("%t: Write 255 Values",$time);
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(negedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			@(negedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end
		@(negedge sysclk);
		$display("%t: Write 255 Values Complete, Check Full",$time);
		check_full;

		// Read 255 Values, Verify Reads
		$display("%t: Read/Verify 255 Values",$time);
		num_errors = 0;
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(negedge sysclk);
			rd_en <= 1'b1;
			@(negedge sysclk);
			rd_en <= 1'b0;
			exp <= in[i];
			@(negedge sysclk);
			@(posedge sysclk);
			expected = {{19{exp[12]}},exp};
			recieved = {{19{dout[12]}},dout};
			if(expected != recieved) 
			begin
				num_errors = num_errors + 1;
				$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);
			end
		end
		if(num_errors == 0) $display("%t: Read/Verified 255 Values Successfullly, Check Empty",$time);
		check_empty;	
		
		// FIFO Reset
		test_reset;

		$display("##### %t: End Task test_rw2 #####",$time);
		
	end
	endtask
	
	task test_reset;
	// This task will test the reset functionality
	begin
		$display("%t: Test Reset ",$time);
		
		@(posedge sysclk);
		rst <= 1'b0;
		repeat(5)@(posedge sysclk);
		rst <= 1'b1;
		repeat(5)@(posedge sysclk);
		if(!empty || full)
		begin
			$display("%t: ERROR: Reset Unsuccessful",$time);
			$stop;
		end
		else
			$display("%t: Reset was Successful",$time);
	end
	endtask

	task check_full;
	// This task will verify that the FIFO is full
	begin
		#5
		if(!full) $display("%t: ERROR: FIFO Not Full",$time);
		else if(empty) $display("%t: ERROR: FIFO Empty", $time);
		else if(!empty && full) $display("%t: FIFO is Full", $time);
	end
	endtask

	task check_empty;
	// This task will verify that the FIFO is empty
	begin
		#5	
		if(full) $display("%t: ERROR: FIFO is Full", $time);
		if(!empty) $display("%t: ERROR: FIFO is not Empty", $time);
		else if(empty && !full) $display("%t: FIFO is Empty",$time);
	end
	endtask
	
	task check_noflag;
	// This task will verify that no flags are set
	begin
		if(full) $display("%t: ERROR: FIFO is Full", $time);
		if(empty) $display("%t: ERROR: FIFO is Empty", $time);
		else if(!full && !empty) $display("%t: No Flags are Set",$time);
	end
	endtask

	task test_error;
	begin
		$display("##### %t: Error Tests #####",$time);
		// Reset FIFO
		repeat(10)@(posedge sysclk);
		test_reset;

		// Write 256 Values
		$display("%t: Write 255 Values",$time);
		repeat(5)@(posedge sysclk);
		for(i=0; i<255; i=i+1)
		begin
			@(posedge sysclk);
			nce <= 1'b0;
			#2 awe <= 1'b0;
			#1 din <= in[i];
			@(posedge sysclk);
			nce <= 1'b1;
			awe <= 1'b1;
		end
		$display("%t: Finish 255 Writes, Check Full",$time);

		check_full;	

		$display("%t: Write an additional Value",$time);
		@(posedge sysclk);
		nce <= 1'b0;
		#2 awe <= 1'b0;
		#1 din <= 13'hABC;
		@(negedge sysclk);
		if(!error)
			$display("%t: An additional write did not cause the error flag",$time);
		else $display("%t: The error flag has risen for write on full",$time);
		@(posedge sysclk);
		nce <= 1'b1;
		awe <= 1'b1;

		// Read one value to check if write was successful
		@(posedge sysclk);
		rd_en <= 1'b1;
		@(posedge sysclk);
		rd_en <= 1'b0;
		expected = {{19{exp[12]}},exp};
		recieved = {{19{dout[12]}},dout};
		if(expected != recieved) 
			$display("%t: ERROR: Expected: %x, Recieved: %x",$time,in[i],dout);

		// Reset FIFO
		repeat(10)@(posedge sysclk);
		test_reset;

		$display("##### %t: Error Tests Complete #####",$time);
		
	end
	endtask

endmodule
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