tb_infifo_rev0.0.v

Verilog jpec coder encoder source code

//////////////////////////////////////////////
//	
//	Module Name:	tb_infifo
//	Description:	Testbench for input fifo.
//	Author:			James Rosenthal
//	Date:			10/28/04
//
//
//	Version	Date		Modifications
//	---------------------------------
//	0.0		10/28/04	Initial
//	0.1		11/20/04	Fit New Design
//
//	///////////////////////////////////////////

`timescale 1ns / 10ps

module tb_infifo();

	reg [12:0] din;
	reg wr_en, rd_en;
	reg rst, clk;

	wire [12:0] dout;
	wire full, empty;

	integer i,j;
	reg [12:0] in [255:0];

	// Instantiate Module
	input_fifo infifo(
		.clk(clk),
		.din(din),
		.wr_en(wr_en),
		.rd_en(rd_en),
		.rst(rst),
		.dout(dout),
		.full(full),
		.empty(empty)
	);

	always #5 clk <= ~clk;

	initial
	begin
		in[0] <= 13'h1fff;
		for(i=1; i<256; i=i+1)
			in[i] <= i;
	end
	
	initial
	begin
		#0 clk <= 1'b0;
		#0 rst <= 1'b0;
		#0 din <= 13'h0;
		#0 wr_en <= 1'b0;
		#0 rd_en <= 1'b0;

		#20 rst <= 1'b1;

		test_reset;
		
		test_full_cont;
		test_full_seq;
		test_empty_cont;
		test_empty_seq;
		
		test_read_empty;
		test_write_full;
	end
	
	task test_reset;
	begin
		@(posedge clk);
		rst <= 1'b0;
		repeat(5)@(posedge clk);
		rst <= 1'b1;
		repeat(5)@(posedge clk);
		if(!empty || full)
		begin
			$display("ERROR: Reset Unsuccessful");
			$stop;
		end
	end
	endtask

	task test_full;
	begin
		if(!full || empty)
		begin
			$display("ERROR: FIFO Should Be Full");
			$stop;
		end
	end
	endtask

	task test_empty;
	begin
		if(!empty || full)
		begin
			$display("ERROR: FIFO Should Be Empty");
			$stop;
		end
	end
	endtask
	
	task test_noflag;
	begin
		if(empty || full)
		begin
			$display("ERROR: FIFO Should Be Neither Full Or Empty");
			$stop;
		end
	end
	endtask
	
	// Test Full Flag with Sequential Writes
	task test_full_seq;
	begin
		$display("********Test Full Flag********");
		$display("******Sequential Writes*******");
		
		test_reset;
		
		// Fill FIFO with 255 Values until Full 
		for(j=0; j<255; j=j+1)
		begin
			@(posedge clk);
			wr_en <= 1'b1;
			din <= in[j];
			@(posedge clk);
			#5 wr_en <= 1'b0;
		end
		
		test_full;	
		
		repeat(100)@(posedge clk);
	end
	endtask

	// Test Full Flag with Continuous Writes
	task test_full_cont;
	begin
		$display("********Test Full Flag********");
		$display("******Continuous Writes*******");
		
		test_reset;
		
		// Fill FIFO with 256 Values until Full
		@(posedge clk);
		wr_en <= 1'b1;
		for(j=0; j<255; j=j+1)
		begin
			din <= in[j];
			@(posedge clk);
		end
		wr_en <= 1'b0;
		repeat(5)@(posedge clk);
		test_full;
		
		repeat(100)@(posedge clk);
	end
	endtask
	
	// Test Empty Flag after Continuous Reads
	task test_empty_cont;
	begin
		$display("********Test Empty Flag********");
		$display("********Continuous Reads*******");
		
		test_reset;
		
		// Fill FIFO with 20 values
		for(j=0; j<20; j=j+1)
		begin
			wr_en <= 1'b1;
			din <= in[j];
			@(posedge clk);
		end
		wr_en <= 1'b0;
		
		test_noflag;
		
		@(posedge clk);
		// Read 20 values and should be empty
		for(j=0; j<20; j=j+1)
		begin
			rd_en <= 1'b1;
			@(posedge clk);
		end
		rd_en <= 1'b0;

		repeat(5)@(posedge clk);
		
		test_empty;

		repeat(100)@(posedge clk);
	end
	endtask

	// Test Empty Flag after Sequential Reads
	task test_empty_seq;
	begin
		$display("********Test Empty Flag********");
		$display("********Sequential Reads*******");

		test_reset;

		// Fill FIFO with 20 values
		for(j=0; j<20; j=j+1)
		begin
			wr_en <= 1'b1;
			din <= in[j];
			@(posedge clk);
		end
		wr_en <= 1'b0;

		test_noflag;

		@(posedge clk);
		// Read 20 Values and Should Be Empty
		for(j=0; j<20; j=j+1)
		begin
			rd_en <= 1'b1;
			@(posedge clk);
			rd_en <= 1'b0;
			repeat(2) @(posedge clk);
		end

		test_empty;

		repeat(100)@(posedge clk);
	end
	endtask
	
	task test_read_empty;
	begin
		$display("********Test Read On Empty*******");

		test_reset;

		@(posedge clk);
		rd_en <= 1'b1;
		@(posedge clk);
		rd_en <= 1'b0;
		
		repeat(5) @(posedge clk);

		////Adjust Pointer and Check Empty
		for(j=0; j<20; j=j+1)
		begin
			wr_en <= 1'b1;
			din <= in[j];
			@(posedge clk);
		end
		wr_en <= 1'b0;

		repeat(5)@(posedge clk);
		
		for(j=0; j<20; j=j+1)
		begin
			rd_en <= 1'b1;
			@(posedge clk);
			rd_en <= 1'b0;
			repeat(2)@(posedge clk);
		end

		test_empty;
		
		@(posedge clk);
		rd_en <= 1'b1;
		@(posedge clk);
		rd_en <= 1'b0;
		
	end
	endtask

	task test_write_full;
	begin
		$display("********Test Write On Full********");

		test_reset;

		// Fill FIFO
		for(j=0; j<256; j=j+1)
		begin
			wr_en <= 1'b1;
			din <= in[j];
			@(posedge clk);
		end
		
		// Write Extra Value
		wr_en <= 1'b0;
		@(posedge clk);
		wr_en <= 1'b1;
		@(posedge clk);
		wr_en <= 1'b0;
		@(posedge clk);
		
		// Check Values for Errors
		for(j=0; j<255; j=j+1)
		begin
			rd_en <= 1'b1;
			@(posedge clk);
			#5 if(dout != in[j])
			begin
				$display("Error: Recieved: %x      Expect: %x",dout,in[j]);
			end
		end
		rd_en <= 1'b0;
		
		repeat(3) @(posedge clk);
		
		test_empty;
		
		repeat(5)@(posedge clk);
		
		// Write 20 Values, Read 20 Values, Sets both Address pointers at
		// new spot
		for(j=0; j<20; j=j+1)
		begin
			wr_en <= 1'b1;
			din <= in[j];
			@(posedge clk);
		end
		wr_en <= 1'b0;

		repeat(5)@(posedge clk);
		
		for(j=0; j<20; j=j+1)
		begin
			rd_en <= 1'b1;
			@(posedge clk);
		end
		rd_en <= 1'b0;

		repeat(5)@(posedge clk);

		test_empty;
		
		repeat(5)@(posedge clk);
		
		// Write 257 Values.
		for(j=0; j<255; j=j+1)
		begin
			wr_en <= 1'b1;
			din <= in[j];
			@(posedge clk);
		end	
		din <= 13'h1fff;
		@(posedge clk);
		wr_en <= 1'b0;

		repeat(5)@(posedge clk);

		// Read Values to See if Correct
		for(j=0; j<255; j=j+1)
		begin
			rd_en <= 1'b1;
			@(posedge clk);
			#5 if(dout != in[j])
				$display("Error: Recieved: %x    Expect: %x",dout,in[j]);
		end
		rd_en <= 1'b0;
		
	end
	endtask


	
endmodule