input_fifo_rev0.1.v

Verilog jpec coder encoder source code

/////////////////////////////////////////////////
//
//  Module Name: 	input_fifo
// 	Descr: 			Synchronous FIFO for Input
// 					Using 256x16 Dual Port BRAM
// 	Author: 		James Rosenthal
// 	Date: 			10/25/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		10/28/04	Initial
// 	0.1		11/8/04		Modular Sections
//
/////////////////////////////////////////////////

`timescale 1ns / 10ps

module input_fifo(
	clk,		// Clock Sync'd for both R&W
	din,		// 13-Bit Data Input
	wr_en,		// Write Enable
	rd_en,		// Read Enable
	rst,		// Active Low Reset
	dout,		// 13-bit Data Output
	full,		// Full Flag
	empty		// Empty Flag
	);

	//
	// Inputs & Outputs
	//
	
	input [12:0] din;	// Data Input
	input wr_en;		// Write Enable
	input rd_en;		// Read Enable
	input rst;			// Active Low Reset
	input clk;			// Input clk
	
	output [12:0] dout; // Data Output
	output full;		// Full Flag
	output empty;		// Empty Flag

	//
	// Registers & Wires
	//
	wire [15:0] doutf;
	wire [7:0] read_addr, write_addr;
	wire empty, full;

	//
	// Behavioral Description
	//
	
	assign dout = doutf[12:0];	
	
	// Empty/Full Flag Generation
	flags flags(
		.read_addr(read_addr),
		.write_addr(write_addr),
	    .empty(empty),
	    .full(full));
	
	// Address Pointers
	addr_ptr addr_ptr(
		.clk(clk),
	    .rst(rst), 
		.write_addr(write_addr), 
		.read_addr(read_addr), 
		.empty(empty), 
		.full(full));
	
	// Instantiate Block RAM
	// A - Write, B - Read
	bram_256x16 infifo(
		.addra(write_addr[7:0]),
		.addrb(read_addr[7:0]),
		.clka(clk),
		.clkb(clk),
		.dina({3'h0,din}),
		.doutb(doutf),
		.enb(rd_en & !empty),
		.sinita(rst),
		.sinitb(rst),
		.wea(wr_en & !full)
	);
	
	
endmodule

module flags(read_addr, write_addr, empty, full)
	
	// 
	// Inputs & Outputs
	//
	
	input [7:0] read_addr, write_addr;
	output empty, full;

	//
	// Module Begin
	//
	
	assign empty = read_addr == write_addr;
	assign full = write_addr > read_addr ? (write_addr - read_addr) == 8'd255 : read_addr - write_addr = 8'd1;
	
endmodule

module addr_ptr(clk, rst, write_addr, read_addr, empty, full);

	//
	// Inputs & Outputs
	//
	
	input clk, rst;
	input empty, full;
	output [7:0] read_addr, write_addr;

	reg [7:0] read_addr, write_addr;

	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			write_addr <= 8'h0;
			read_addr <= 8'h0;
		end
		// read, not empty
		else if(rd_en && !wr_en && !empty)
			read_addr <= read_addr + 8'h1;
		// write, not full
		else if(wr_en && !rd_en && !full)
			write_addr <= write_addr + 8'h1;
		// simulataneous read/write, address pointers don't match
		else if(read_addr != write_addr && wr_en && rd_en)
		begin
			write_addr <= write_addr + 8'h1;
			read_addr <= read_addr + 8'h1;
		end
	end
	
endmodule