read_sm_rev0.0.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////
//
//  Module Name: 	read_sm
// 	Descr: 			State Machine to Read from 
// 					FIFO with Two Clock Domains
// 	Author: 		James Rosenthal
// 	Date: 			11/15/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		11/15/04	Initial
//
//
////////////////////////////////////////////////////

`timescale 1ns / 10ps

module read_sm(
	extclk,		// External Clock
	sysclk,		// System Clock
	rst,		// Active Low Reset
	empty,		// FIFO Empty
	rd_en,		// Read Enable
	rd_fifo,	// Read FIFO Enable
	din,		// Data input
	dout,		// Data output
	error		// Invalid Write
	);
	
	// 
	// Inputs & Outputs
	//

	input [12:0] din;	// Data Input	
	input extclk;		// External Clock
	input sysclk;		// System Clock
	input rst;			// Asynchronous Actie Low Reset
	input rd_en;		// Read Enable
	input empty;		// FIFO Empty
	
	output [12:0] dout;	// Data Output
	output [1:0] error;	// Invalid Read
	output rd_fifo;		// Read FIFO


	//
	// Parameters
	//
	
	parameter IDLE	= 5'h1;			// Start Read FIFO if Empty
	parameter READFIFO1 = 5'h2;		// Read Enable to FIFO
	parameter READFIFO2	= 5'h4;		// Read Data from FIFO
	parameter WAIT1 = 5'h8;			// Wait for Read Signal 
	parameter WAIT2 = 5'h16;		// Wait for Read Finish
	
	//
	// Wires & Registers
	//
	
	reg [12:0] sdata;	// Data Latched on sysclk
	
	reg rd_fifo;		// FIFO Read Enable
	reg [1:0] error;	// Error Output {Read_Empty,Read_in_Progress}
	reg [12:0] dout;	// 13-bit Output
	
	reg [4:0] state;	// State Register
	reg [4:0] nstate;	// Next State Register
	
	//
	// Behavioral Description
	// 
	
	// State Transitions
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
			state <= IDLE;
		else state <= nstate;
	end
	
	// State Behaviors
	always @ (negedge sysclk or negedge rst)
	begin
		if(!rst)
		begin
			rd_fifo <= 1'b0;
			sdata <= 13'h0;
			nstate <= IDLE;
		end
		else
		begin
			case(state)
				
				IDLE:
				begin
					rd_fifo <= 1'b0;
					nstate <= !empty ? READFIFO1 : IDLE;
				end
				
				READFIFO1:
				begin
					rd_fifo <= 1'b1;
					nstate <= READFIFO2;
				end
				
				READFIFO2: 
				begin
					rd_fifo <= 1'b0;
					sdata <= din;
					nstate <= WAIT1;
				end
				
				WAIT1:
				begin
					rd_fifo <= 1'b0;
					nstate <= rd_en ? WAIT2 : WAIT1;
				end

				WAIT2:
					nstate <= rd_en ? WAIT2 : IDLE;
				
			endcase
		end
	end

	// Error Flag
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
			error <= 2'b0;
		else
		begin
			error[1] <= rd_en && state == IDLE; // Read on Empty
			error[0] <= rd_en && (!state[4:3]); // Read In Progress
		end
	end

endmodule