write_sm_rev0.1.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////
//
//  Module Name: 	write_sm
// 	Descr: 			State Machine to Write to 
// 					FIFO with Two Clock Domains
// 	Author: 		James Rosenthal
// 	Date: 			11/12/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		11/12/04	Initial
// 	0.1		11/19/04	Change To SM Format
//
////////////////////////////////////////////////////

`timescale 1ns / 10ps

module write_sm(
	sysclk,		// System Clock
	rst,		// Active Low Reset
	en,			// Write Enable
	full,		// FIFO Full Status
	din,		// Data input
	dout,		// Data output
	doe,		// Data Ouput Enable
	error		// Invalid Write
	);
	
	// 
	// Inputs & Outputs
	//

	input [12:0] din;	// Data Input	
	input sysclk;		// System Clock
	input rst;			// Asynchronous Actie Low Reset
	input en;			// Enable State Machine
	input full;			// FIFO full status
	
	output [12:0] dout;	// Data Output:1
	
	output doe;			// Data Output Enable
	output error;		// Invalid Write

	//
	// Wires & Registers
	//
	
	reg [12:0] dout;
	reg doe;
	reg error;			// Invalid Write
	reg [1:0] state, nstate;
	
	//
	// Parameters
	//
	
	parameter IDLE = 2'h1;
	parameter WRITE = 2'h2;
	
	//
	// Behavioral Description
	//
	
	// State Register Update
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst) state <= IDLE;
		else state <= nstate;
	end
	
	// State Machine Behavior
	always @ (negedge sysclk or negedge rst)
	begin
		if(!rst)
		begin
			nstate <= IDLE;
			doe <= 1'b0;
			dout <= 13'h0;
		end
		else 
		begin
			case(state)
				IDLE: 
				begin
					nstate <= en ? WRITE : IDLE;
					doe <= 1'b0;
				end
				WRITE:
				begin
					dout <= din;
					doe <= 1'b1;
					nstate <= IDLE;
				end
			endcase
		end
	end

	// Error Flag 
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
			error <= 1'b0;
		else 
			error <= en && full;
	end
	
endmodule