input_fifo_rev0.5.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////
//
//  Module Name: 	input_fifo
// 	Descr: 			Input FIFO Control 
// 	Author: 		James Rosenthal
// 	Date: 			10/25/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		10/28/04	- Initial
// 	0.1		11/08/04	- Modular Sections
// 	0.2		11/12/04	- FIFO Control as Top Level
// 						- Write State Machines
// 						- Error Output Added
//	0.3		11/27/04	- Changed to Fit FIFO SM rev 0.2
//						- Remove extclk, add awe and nce
//						- Remove wr_en					
//	0.4		12/09/04	- Removed nce and awe. Add wr_en.
//	0.5		12/20/04	- Added Write State as Output to
//						  provide visibility at higher
//						  level modules.  
//						- Added Read/Write Pointers as
//						  outputs to provide visibilty
//						  at higher level modules.
//						- Inverted Clock to FIFO
//
//  Notes
//  -----
//  			Input FIFO
//  				 ||
//			|-------------------|
//  	Write SM	 		Low Level FIFO
//  							|
//  			|---------------|---------------|
//  		  Flags			  BRAM			Addr Ptrs
//  		  
//  - Hierarchy in this FIFO is modularize the FIFO 
//  control and functionality.  
//
//	- Write Enable for the FIFO is driven by the state machine.
//	- Read Enable is driven externally by a state machine.  
//		+ That SM may be better instantiated in this module
//
////////////////////////////////////////////////////

`timescale 1ns / 10ps

module input_fifo(	// Higher Level FIFO Control Module
	sysclk, 	// System Clock From FPGA
	wr_en,		// Asynchronous Write Enable
	rd_en,		// Asynchronous Read Enable
	din, 		// 13-bit Data Input
	dout, 		// 13-bit Data Output
	full, 		// Full Flag
	empty,		// Empty Flag
	rst,		// Active Low Reset
	error,		// Error on Read or Write
	wr_state,	// Write State Machine Current State
	raddr,		// Read Address Pointer
	waddr		// Write Address Pointer
	);

	// 
	// Inputs & Outputs
	//
	
	input [12:0] din;	// Data Input
	input sysclk;		// System Clock (25MHz)
	input rd_en;		// Asynchronous Read Enable
	input wr_en;		// Asynchronous Write Enable
	input rst;			// Active Low Reset

	output [12:0] dout;	// 13-bit Data Output
	output [ 7:0] raddr;// Read Address Pointer
	output [ 7:0] waddr;// Write Address Pointer
	output empty;		// Empty Flag
	output full;		// Full Flagrd_fifo <= 1'b0;
	output error;		// Invalid Write Occurred
	output wr_state;	// Write State Machine Current State

	wire [ 7:0] raddr, waddr;

	//
	// Behavioral Description
	// 

	// Instantiate Write State Machine
	// Write to FIFO
	write_sm write_sm(
		.sysclk(sysclk),
		.rst(rst),
		.wr_en(wr_en),
		.full(full),
		.fifo_wr_en(fifo_wr_en),
		.error(error),
		.state(wr_state)
	);
	
	// Instantiate FIFO
	fifo ififo(
		.clk(!sysclk),
		.din(din),
		.wr_en(fifo_wr_en),
		.rd_en(rd_en),
		.rst(rst),
		.dout(dout),
		.full(full),
		.empty(empty),
		.raddr(raddr),
		.waddr(waddr)
	);
	
endmodule