write_sm_rev0.5.v

Verilog jpec coder encoder source code

//////////////////////////////////////////////////////////
//
//  Module Name: 	write_sm
// 	Descr: 			State Machine to Write to 
// 					FIFO with Two Clock Domains
// 	Author: 		James Rosenthal
// 	Date: 			11/12/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		11/12/04	- Initial
// 	0.1		11/19/04	- Change To SM Format
// 	0.2		11/25/04	- Remove Data Output
// 						- Data is handled externally
// 						- Input awe and ce added 
// 						  in place of enable
// 						- Error Flag is Now Combinational
// 	0.3		12/06/04	- Change doe to fifo_wr_en	
// 	0.4		12/09/04	- Remove awe,nce, add wr_en.
// 	0.5		12/20/04	- Added state as an output for
// 						  visibility from higher level
// 						  modules
// 	
/////////////////////////////////////////////////////////

`timescale 1ns / 10ps

module write_sm(
	sysclk,		// System Clock
	rst,		// Active Low Reset
	wr_en,		// Asynchronous Write Enable
	full,		// FIFO Full Status
	fifo_wr_en,	// Data Ouput Enable
	error,		// Invalid Write
	state		// Current State of Machine
	);
	
	// 
	// Inputs & Outputs
	//

	input sysclk;		// System Clock
	input rst;			// Asynchronous Actie Low Reset
	input wr_en;		// Asynchronous Write Enable
	input full;			// FIFO full status
	
	output fifo_wr_en;	// Data Output Enable
	output error;		// Invalid Write
	output state;		// Current State of Machine

	//
	// Wires & Registers
	//
	
	reg fifo_wr_en;
	reg state, nstate;

	wire error;			// Invalid Write
	
	//
	// Parameters
	//
	
	parameter IDLE = 1'b0;
	parameter WRITE = 1'b1;
	
	//
	// Behavioral Description
	//
	
	assign error = wr_en && full;
	
	// State Register Update
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst) state <= IDLE;
		else state <= nstate;
	end
	
	// State Machine Behavior
	always @ (negedge sysclk or negedge rst)
	begin
		if(!rst)
		begin
			nstate <= IDLE;
			fifo_wr_en <= 1'b0;
		end
		else 
		begin
			case(state)
				IDLE: 
				begin
					nstate <= wr_en ? WRITE : IDLE;
					fifo_wr_en <= wr_en ? 1'b1 : 1'b0;
				end
				WRITE:
				begin
					fifo_wr_en <= 1'b0;
					nstate <= !wr_en ? IDLE : WRITE;
				end
			endcase
		end
	end

endmodule