read_sm_rev0.5.v

来自「Verilog jpec coder encoder source code」· Verilog 代码 · 共 156 行

////////////////////////////////////////////////////////////
//
//  Module Name: 	read_sm
// 	Descr: 			State Machine to Read from 
// 					FIFO with Two Clock Domains
// 	Author: 		James Rosenthal
// 	Date: 			11/15/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		11/15/04	- Initial
//	0.1		11/27/04	- Reduce to 1 Wait State
//						- Add Transition from Wait to Read
//						- Remove extclk from module
//						- Remove rd_en, add are, and nce
//	0.2		12/5/04		- Remove one read state as timing
//						  is inaccurate.
//						- Now only read on empty error is 
//						  possible.
//						- sdata is actually dout. 
//						- error flag is combinational
//						- Add rd_fifo2 to avoid evaluating
//						  a reg, the same time it updates.
//	0.3		12/09/04	- Remove are, nce, and add rd_en.
//	0.4		12/20/04	- Add state as an output to gain
//						  visibility at higher level modules
//						
////////////////////////////////////////////////////////////

`timescale 1ns / 10ps

module read_sm(
	sysclk,		// System Clock
	rst,		// Active Low Reset
	empty,		// FIFO Empty
	rd_en,		// Asynchronous Read Enable
	rd_fifo,	// Read FIFO Enable
	din,		// Data input
	dout,		// Data output
	error,		// Invalid Write
	state		// Current State of Machine
	);
	
	// 
	// Inputs & Outputs
	//

	input [12:0] din;	// Data Input	
	input sysclk;		// System Clock
	input rst;			// Asynchronous Actie Low Reset
	input rd_en;		// Asynchronous Read Enable
	input empty;		// FIFO Empty
	
	output [12:0] dout;	// Data Output
	output error;		// Read on Empty
	output rd_fifo;		// Read FIFO
	output [ 3:0] state;// Current State Of Machine


	//
	// Parameters
	//
	
	parameter IDLE	= 3'h1;			// Start Read FIFO if Empty
	parameter READFIFO = 3'h2;		// Store Data from FIFO
	parameter WAIT = 3'h4;			// Wait for read cycle to end
	
	//
	// Wires & Registers
	//
	
	reg rd_fifo;		// FIFO Read Enable
	reg rd_fifo2;		// Positive edge rd_fifo
	reg [12:0] dout;	// 13-bit Output
	
	reg [2:0] state;	// State Register
	reg [2:0] nstate;	// Next State Register

	wire error;			// Error - Read on Empty
	//
	// Behavioral Description
	// 
	
	// State Transitions
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
			state <= IDLE;
		else
		begin
			state <= nstate;
			rd_fifo2 <= rd_fifo;
		end
		
	end
	
	// State Behaviors
	always @ (negedge sysclk or negedge rst)
	begin
		if(!rst)
		begin
			rd_fifo <= 1'b0;
			dout <= 13'h0;
			nstate <= IDLE;
		end
		else
		begin
			case(state)
				
				IDLE:
				// When FIFO is not empty, store one value
				// into temporary reg for dsp to read on 
				// request.
				begin
					rd_fifo <= !empty;
					nstate <= !empty ? READFIFO : IDLE;
				end
				
				READFIFO:
				// Store data into temporary register dout
				// Wait for a DSP cycle to start, then 
				// transition to WAIT state.  
				begin
					if(rd_fifo2)
						dout <= din;
					rd_fifo <= 1'b0;
			//		nstate <= rd_en ? WAIT : READFIFO;
					nstate <= rd_en ? WAIT : READFIFO;
				end
				
				WAIT:
				// Wait for DSP cycle to finish read.  If
				// DSP cycle finished, and fifo still not 
				// empty, enable rd_fifo, and move to 
				// READFIFO state.
				begin
					rd_fifo <= !rd_en & !empty;
					nstate <= rd_en ? WAIT : 
						!empty ? READFIFO : IDLE;
				end
/*				
				default:
				begin
					nstate <= WAIT;
				end
				*/
			endcase
		end
	end

	// Error Flag
	assign error = rd_en && state == IDLE;

endmodule