fifo_test_rev0.0.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////////////////
//
//  Module Name: 	fifo_test
// 	Descr: 			FIFO Implementation Test
// 	Author: 		James Rosenthal
// 	Date: 			12/07/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		12/07/04	- Initial
//
//
// 	Module Description
// 	------------------
//  This module will implement both the input and output fifo, 
//  to interface the fpga to the dsp.  The input fifo is to 
//  accept writes from the dsp, as the output fifo is used to 
//  read data back to the fpga.  
//
//  The read/write addresses are defined below.
//
//  write address 0x0 - write to input fifo
//  write address 0x1 - no-op instruction
//  read address 0x0 - read from output fifo
//  read address 0x1 - read from input fifo, write to output fifo
//
//  Rearranging the data will put the 4LSB, to bits [11:8]
//  
////////////////////////////////////////////////////////////////

`timescale 1ns / 10ps

module fifo_test(
	sysclk,		// FPGA clock
	rst,		// Async. Active Low Reset
	nce,		// Active Low Chip Enable
	are,		// Async. Active Low Read Enable
	awe,		// Async. Active Low Write Enable
	data,		// Data bus 
	addr		// Address Bus 
);

	//
	// Inputs & Outputs
	//
	
	input sysclk;	// FPGA Clock - 25MHz
	input rst;		// Async. Active Low Reset
	input nce;		// Active Low Chip Enable
	input are;		// Async. Active Low Read Enable
	input awe;		// Async. Active Low Write Enable

	inout [18:0] data;	// Data Bus 
	input addr;	// Address Bus
	
	//
	// Registers & Wires
	//
	
	wire doe;	// Data Output Enable for Tristate

	wire [12:0] odout; // Data Output of Output FIFO
	wire [12:0] idout; // Data Output of Input FIFO
	
	wire ifull;		// Input FIFO is Full
	wire iempty;	// Input FIFO is Empty
	wire ierror;	// Input FIFO Error - Write on Full
	wire ofull;		// Output FIFO Full
	wire oempty;	// Output FIFO Empty
	wire oerror;	// Output FIFO Error - Read on Empty

	wire [5:0] status;	// Flag Status

	wire iwr_en, ird_en;	// Input FIFO Read/Write Enables
	wire ord_en;			// Output FIFO Read Enables
	reg owr_en;				// Output FIFO Write Enable
	
	// 
	// Instantiate Input FIFO
	//
	
	input_fifo input_fifo(
		.sysclk(sysclk),
		.wr_en(iwr_en),
		.rd_en(ird_en),
		.din(data[12:0]),
		.dout(idout),
		.full(ifull),
		.empty(iempty),
		.rst(rst),
		.error(ierror)
	);
	
	//
	// Instantiate Output FIFO
	//
	
	output_fifo output_fifo(
		.sysclk(sysclk),
		.rst(rst),
		.rd_en(ord_en),
		.wr_en(owr_en),
		.din({idout[12],idout[3:0],idout[11:4]}),
		.dout(odout),
		.full(ofull),
		.empty(oempty),
		.error(oerror)
	);

	// 
	// Behavioral Description
	//
	
	// Status Flags
	assign status = {ifull, iempty, ierror, ofull, oempty, oerror};
	
	// Data Bus 
	assign doe = ~nce && ~are;
	assign data = doe ? {status,odout} : 19'bz;

	// Write/Read Enables
	assign iwr_en = ~nce && ~awe && (addr == 2'h0);
	assign ird_en = ~nce && ~are && (addr == 2'h1);
	assign ord_en = ~nce && ~are && (addr == 2'h0);
	
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst) owr_en <= 1'b0;
		else owr_en <= ird_en;
	end	

endmodule