fifo_test_rev0.5.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////////////////
//
//  Module Name: 	fifo_test
// 	Descr: 			FIFO Implementation Test
// 	Author: 		James Rosenthal
// 	Date: 			12/07/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		12/07/04	- Initial
//	0.1		12/13/04	- Add another address bit for an
//						  addressable reset, and to read 
//						  status flags without affecting 
//						  the rest of the design.
//	0.2		12/20/04	- Added Visibity to see the current
//						  state fof the read and write
//						  state machines, and to see the
//						  address pointers of either fifo.
//						  Requires an additional Address bit.
//	0.5		02/14/05	- No Changes. Rev'd to match other 
//						  modules
//
// 	Module Description
// 	------------------
//  This module will implement both the input and output fifo, 
//  to interface the fpga to the dsp.  The input fifo is to 
//  accept writes from the dsp, as the output fifo is used to 
//  read data back to the fpga.  
//
//  The read/write addresses are defined below.
//
//  write address 0x0 - write to input fifo
//  write address 0x1 - no-op instruction
//  write address 0x2 - reset
//  write address 0x3 - ?
//  write address 0x4 - ?
//  read address 0x0 - read from output fifo
//  read address 0x1 - read from input fifo, write to output fifo
//  read address 0x2 - read status reg
//  read address 0x3 - Read Input FIFO, {SM CS, RADDR, WADDR}
//  read address 0x4 - Read Output FIFO {SM CS, RADDR, WADDR}
//  
////////////////////////////////////////////////////////////////

`timescale 1ns / 10ps

module fifo_test(
	sysclk,		// FPGA clock
	fpgarst,	// Async. Active Low Reset
	nce,		// Active Low Chip Enable
	are,		// Async. Active Low Read Enable
	awe,		// Async. Active Low Write Enable
	data,		// Data bus 
	addr		// Address Bus 
);

	//
	// Inputs & Outputs
	//
	
	input sysclk;	// FPGA Clock - 25MHz
	input fpgarst;	// Async. Active Low Reset
	input nce;		// Active Low Chip Enable
	input are;		// Async. Active Low Read Enable
	input awe;		// Async. Active Low Write Enable

	inout [18:0] data;	// Data Bus 
	input [2:0] addr;	// Address Bus
	
	//
	// Registers & Wires
	//
	
	wire rst;	// Reset to FIFO Modules
	wire soft;	// Soft Reset via Write to address 0x2

	wire doe;	// Data Output Enable for Tristate

	wire [12:0] odout; // Data Output of Output FIFO
	wire [12:0] idout; // Data Output of Input FIFO
	
	wire ifull;		// Input FIFO is Full
	wire iempty;	// Input FIFO is Empty
	wire ierror;	// Input FIFO Error - Write on Full
	wire ofull;		// Output FIFO Full
	wire oempty;	// Output FIFO Empty
	wire oerror;	// Output FIFO Error - Read on Empty

	wire [5:0] status;	// Flag Status

	wire iwr_en, ird_en;	// Input FIFO Read/Write Enables
	wire ord_en;			// Output FIFO Read Enables
	reg owr_en, owr_ena;	// Output FIFO Write Enable

	wire wr_state;			// Write State Machine Current State
	wire [2:0] rd_state;	// Read State Machine Current State
	
	wire [7:0] iraddr, oraddr; // Read Address Pointers
	wire [7:0] iwaddr, owaddr; // Write Address Pointers

	reg [12:0] odin;	// Data Input to Output FIFO
	reg rd_en, start_read;

	// 
	// Instantiate Input FIFO
	//
	
	input_fifo input_fifo(
		.sysclk(!sysclk),
		.wr_en(iwr_en),
		.rd_en(rd_en),
		.din(data[12:0]),
		.dout(idout),
		.full(ifull),
		.empty(iempty),
		.rst(rst),
		.error(ierror),
		.wr_state(wr_state),
		.raddr(iraddr),
		.waddr(iwaddr)
	);
	
	//
	// Instantiate Output FIFO
	//
	
	output_fifo output_fifo(
		.sysclk(sysclk),
		.rst(rst),
		.rd_en(ord_en),
		.wr_en(owr_en),
		.din(odin),
		.dout(odout),
		.full(ofull),
		.empty(oempty),
		.error(oerror),
		.rd_state(rd_state),
		.raddr(oraddr),
		.waddr(owaddr)
	);

	// 
	// Behavioral Description
	//
	
	// Reset
	assign soft = nce || awe || !addr[1] || addr[0];
	assign rst = fpgarst && soft;
	
	// Status Flags
	assign status = {ifull, iempty, ierror, ofull, oempty, oerror};
	
	// Data Bus 
	assign doe = ~nce && ~are;
	assign data = doe && addr == 3'h1 ? {15'h0,status[5:4],status[2:1]} : 19'bz;
	assign data = doe && addr == 3'h2 ? {15'h0,status[5:4],status[2:1]} :  19'bz;
	assign data = doe && addr == 3'h3 ? {2'h0, wr_state, iraddr, iwaddr} : 19'bz;
	assign data = doe && addr == 3'h4 ? {rd_state,oraddr,owaddr} : 19'bz;
	assign data = doe && (addr != 3'h1 && addr != 3'h2 && addr != 3'h3 && addr != 3'h4 && addr != 3'h7) ? {status,odout} : 19'bz;
	assign data = doe && addr == 3'h7 ? {6'h2a,odin} : 19'bz;

	// Write/Read Enables
	assign iwr_en = ~nce && ~awe && (addr == 3'h0);
	assign ird_en = ~nce && ~are && (addr == 3'h1);
	assign ord_en = ~nce && ~are && (addr == 3'h0);

	always @ (negedge sysclk or negedge rst)
	begin
		if(!rst)
		begin
			rd_en <= 1'b0;
			start_read <= 1'b0;
		end
	  	else if(ird_en && !start_read)
		begin
			rd_en <= 1'b1;
			start_read <= 1'b1;
		end
		else if(ird_en && start_read)
			rd_en <= 1'b0;
		else if(!ird_en && start_read)
		begin
			rd_en <= 1'b0;
			start_read <= 1'b0;
		end
		else
		begin
			rd_en <= 1'b0;
			start_read <= 1'b0;
		end  
	end

	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
		   owr_en <= 1'b0;
		else
		begin
			owr_ena <= rd_en;
			owr_en <= owr_ena;
		end
	end	

	always @ (negedge sysclk or negedge rst)
	begin
		if(!rst)
			odin <= 13'h0;
		else if(owr_ena) 
			odin <= idout;
	end

endmodule