write_sm_rev0.0.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////
//
//  Module Name: 	write_sm
// 	Descr: 			State Machine to Write to 
// 					FIFO with Two Clock Domains
// 	Author: 		James Rosenthal
// 	Date: 			11/12/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		11/12/04	Initial
//
////////////////////////////////////////////////////

`timescale 1ns / 10ps

module write_sm(
	extclk,		// External Clock
	sysclk,		// System Clock
	rst,		// Active Low Reset
	en,			// Write Enable
	din,		// Data input
	dout,		// Data output
	doe,		// Data Ouput Enable
	error		// Invalid Write
	);
	
	// 
	// Inputs & Outputs
	//

	input [12:0] din;	// Data Input	
	input extclk;		// External Clock
	input sysclk;		// System Clock
	input rst;			// Asynchronous Actie Low Reset
	input en;			// Enable State Machine
	
	output [12:0] dout;	// Data Output
	output doe;			// Data Output Enable
	output error;		// Invalid Write

	//
	// Wires & Registers
	//
	reg [12:0] edata;	// Temp Storage for Data (External)
	reg [12:0] sdata;	// Temp Storage for Data (System)
	reg etoggle;		// Toggle bit to verify valid data
	reg stoggle;		// Toggle bit to verify valid data
	reg error;			// Invalid Write
	
	//
	// Behavioral Description
	//
	
	// Latch Data on External Clock
	always @ (posedge extclk or negedge rst)
	begin
		if(!rst)
		begin
			edata <= 12'h0;
			etoggle <= 1'b0;
			error	<= 1'b0;
		end
		else if(en && !ready && etoggle == stoggle)
		begin
			edata <= din;
			etoggle <= !etoggle;
		end
		else if(en) 
			error <= 1'b1;
		else 
			error <= 1'b0;
	end	

	// Double Buffer Data with System Clock
	always @ (posedge sysclk or negedge rst)
	begin
		if(!rst)
		begin
			sdata <= 1'h0;
			doe <= 1'h0;	
			stoggle <= 1'h0;
		end
		else if(stoggle != etoggle)
		begin
			sdata <= edata;
			doe <= 1'b1;
			stoggle <= !stoggle;
		end	
		else
			doe <= 1'b0;
	end
	
endmodule