output_fifo_rev0.5.v

Verilog jpec coder encoder source code

////////////////////////////////////////////////////////
//
//  Module Name: 	output_fifo
// 	Descr: 			Output FIFO Control 
// 	Author: 		James Rosenthal
// 	Date: 			11/15/04
//
//
// 	Version	Date		Modifications
// 	---------------------------------
// 	0.0		11/15/04	- Initial 
// 	0.1		12/06/04	- Update to Fit read_sm
// 						- Fill in FIFO I/O
// 						- Remove extclk as it is unused
// 						- Remove rd_en and add are, nce
// 	0.2		12/09/04	- Remove are, nce, add rd_en
// 	0.3		12/20/04	- Added Read State Machine
// 						  Current State as an Output
// 						  to gain visibilty at higher
// 						  level modules.
// 						- Added Read/Write Pointers as
// 						  outputs to gain visibility at 
// 						  higher level modules.
//
////////////////////////////////////////////////////////

`timescale 1ns / 10ps

module output_fifo(
	sysclk,		// FPGA System Clock
	rst,		// Asynchronous Active Low Reset
	rd_en,		// Asynchronous Read Enable
	wr_en,		// Write Enable
	din,		// Data Input
	dout,		// Data Output
	full,		// Full Flag
	empty,		// Empty Flag
	error,		// Error on Read or Write
	rd_state,	// Read State Machine CS
	raddr,		// Read Address Pointer
	waddr		// Write Address Pointer
);

	//
	// Inputs & Outputs
	//
	
	input sysclk;		// System Clock
	input rst;			// Asynchronous Active Low Reset
	input wr_en;		// Write Enable
	input rd_en;		// Asynchronous Read Enable
	
	input [12:0] din;	// Data Input

	output [12:0] dout;	// Data Output
	output full;		// Full Flag
	output empty;		// Empty Flag
	output error;		// Invalid Read to FIFO
	output [2:0] rd_state;	// Read State Machine CS
	output [7:0] raddr;	// Read Address Pointer
	output [7:0] waddr;	// Write Address Pointer

	//
	// Registers & Wires
	//
	
	wire [12:0] dout;		// Data Output
	wire [12:0] fifo_dout;	// FIFO Data Output
	wire [7:0] raddr, waddr;// Read/Write Address Ptrs
	
	//
	// Behavioral Description
	//
	
	// Instantiate Read State Machine
	read_sm read_sm(
		.sysclk(sysclk),
		.rst(rst),
		.empty(empty),
		.rd_en(rd_en),
		.rd_fifo(rd_fifo),
		.din(fifo_dout),
		.dout(dout),
		.error(error),
		.state(rd_state)
	);
	
	// Instantiate FIFO
	fifo ofifo(
		.clk(sysclk),
		.din(din),
		.wr_en(wr_en),
		.rd_en(rd_fifo),
		.rst(rst),
		.dout(fifo_dout),
		.full(full),
		.empty(empty),
		.raddr(raddr),
		.waddr(waddr)
	);
	

endmodule