tb_enc_rev1.v
来自「Verilog jpec coder encoder source code」· Verilog 代码 · 共 902 行 · 第 1/2 页
V
902 行
#0 crle[58] <= 12'h000;
#0 crle[59] <= 12'h000;
#0 crle[60] <= 12'h000;
#0 crle[61] <= 12'h000;
#0 crle[62] <= 12'h000;
#0 crle[63] <= 12'h000;
#0 chuff[0] <= 12'h003;
#0 chuff[1] <= 12'h004;
#0 chuff[2] <= 12'h002;
#0 chuff[3] <= 12'h002;
#0 chuff[4] <= 12'h001;
#0 chuff[5] <= 12'h001;
#0 chuff[6] <= 12'h011;
#0 chuff[7] <= 12'h002;
#0 chuff[8] <= 12'h041;
#0 chuff[9] <= 12'h021;
#0 chuff[10] <= 12'h0a1;
#0 chuff[11] <= 12'h000;
#0 oc[0] <= 20'h000d8;
#0 oc[1] <= 20'h00091;
#0 oc[2] <= 20'h0006e;
#0 oc[3] <= 20'h00075;
#0 oc[4] <= 20'h000af;
#0 oc[5] <= 20'h000c0;
#0 ocrle[0] <= 20'h7fb03;
#0 ocrle[1] <= 20'h00904;
#0 ocrle[2] <= 20'h00302;
#0 ocrle[3] <= 20'h00302;
#0 ocrle[4] <= 20'h7fe01;
#0 ocrle[5] <= 20'h00101;
#0 ocrle[6] <= 20'h00111;
#0 ocrle[7] <= 20'h7fc02;
#0 ocrle[8] <= 20'h7fe41;
#0 ocrle[9] <= 20'h00121;
#0 ocrle[10] <= 20'h001a1;
#0 ocrle[11] <= 20'h00000;
#0 clk <= 1'b0;
#0 rst <= 1'b0;
#0 lc <= 1'b0;
#0 dstrb <= 1'b0;
#0 addr <= 4'h0;
#0 din <= 12'h0;
#17 rst <= 1'b1;
// wait awhile
repeat(150) @(posedge clk);
// Luminance Block Tests
// in out
test_addr0; // fdct huff
test_addr4; // qnr huff
test_addr8; // rle huff
test_addrC; // huff huff
test_addr1; // fdct rle
test_addr2; // fdct qnr
test_addr3; // fdct fdct
test_addr5; // qnr rle
test_addr6; // qnr qnr
test_addr9; // rle rle
// All other addresses do not make sense
// Chrominance Block Tests
lc <= 1'b1;
test_addr0;
test_addr4;
test_addr8;
test_addrC;
test_addr1;
test_addr2;
test_addr3;
test_addr5;
test_addr6;
test_addr9;
$stop;
end
// Display Outputs
always @ (posedge clk or negedge rst)
begin
if(~rst)
begin
err = 0;
cnt = 0;
j <= 1'b0;
end
else if(!j && doe && addr[1])
j <= 1'b1;
else if(j && cnt < 63)
begin
cnt <= cnt + 1;
if(verbose) $display("%d:DOUT = %x",cnt,dout);
case(addr[1:0])
2'h2:
begin
if(~lc && irle[cnt] != {dout[10],dout[10:0]})
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,irle[cnt],dout);
end
else if(lc && crle[cnt] != {dout[10],dout[10:0]})
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,crle[cnt],dout);
end
end
2'h3:
begin
if(!lc && iqnr[cnt] != dout[11:0])
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,iqnr[cnt],dout);
end
else if(lc && cqnr[cnt] != dout[11:0])
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,cqnr[cnt],dout);
end
end
endcase
end
else if(j && cnt == 63)
begin
cnt <= 6'h0;
j <= 1'b0;
if(verbose) $display("%d:DOUT = %x",cnt,dout);
case(addr[1:0])
2'h2:
begin
if(!lc && irle[cnt] != {dout[10],dout[10:0]})
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,irle[cnt],dout);
end
else if(lc && crle[cnt] != {dout[10],dout[10:0]})
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,crle[cnt],dout);
end
end
2'h3:
begin
if(!lc && iqnr[cnt] != dout[11:0])
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,iqnr[cnt],dout);
end
else if(lc && cqnr[cnt] != dout[11:0])
begin
err = err + 1;
$display("%d:ERROR Expected: %x Recieved: %x",cnt,cqnr[cnt],dout);
end
end
endcase
end
else if(doe)
begin
case(addr[1:0])
2'h0:
begin
cnt <= cnt + 1;
if(~lc && ol[cnt] != dout)
begin
$display("%d:ERROR Expected: %x Recieved: %x",cnt,ol[cnt],dout);
err = err + 1;
end
else if(lc && oc[cnt] != dout)
begin
$display("%d:ERROR Expected: %x Recieved: %x",cnt,oc[cnt],dout);
err = err + 1;
end
else if(verbose) $display("%d:DOUT = %x",cnt,dout);
end
2'h1:
begin
cnt <= cnt + 1;
if(!lc && orle[cnt] != dout)
begin
$display("%d:ERROR Expected: %x Recieved: %x",cnt,orle[cnt],dout);
err = err + 1;
end
if(lc && ocrle[cnt] != dout)
begin
$display("%d:ERROR Expected: %x Recieved: %x",cnt,ocrle[cnt],dout);
err = err + 1;
end
else if(verbose) $display("%d:DOUT = %x",cnt,dout);
end
endcase
end
end
// Address = 0x0000
// FDCT_in, HUFF_out
task test_addr0;
begin
$display("********************************");
$display("Testing Address = 0x0000");
$display("********************************");
addr <= 4'h0;
dstrb <= #1 1'b1;
@(posedge clk);
dstrb <= #1 1'b0;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 cl[i] - 12'd128;
else din = #1 il[i] - 12'd128;
@(posedge clk);
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address = 0x0100
// QNR in, HUFF out
task test_addr4;
begin
$display("********************************");
$display("Testing Address = 0x0100");
$display("********************************");
addr <= 4'h4;
dstrb <= #1 1'b1;
@(posedge clk);
dstrb <= #1 1'b0;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 cqnr[i];
else din = #1 iqnr[i];
@(posedge clk);
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address 0x1000
// RLE in, HUFF out
task test_addr8;
begin
$display("********************************");
$display("Testing Address = 0x1000");
$display("********************************");
addr <= 4'h8;
dstrb <= #1 1'b1;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 crle[i];
else din = #1 irle[i];
@(posedge clk);
dstrb <= #1 1'b0;
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address = 0x1100
// HUFF in, HUFF out
task test_addrC;
begin
$display("********************************");
$display("Testing Address = 0x1100");
$display("********************************");
addr <= 4'hC;
dstrb <= #1 1'b1;
if(lc)
begin
for(i=0; i<12; i=i+1)
begin
dstrb <= #1 1'b1;
din = #1 chuff[i];
@(posedge clk);
dstrb <= #1 1'b0;
repeat(1)@(posedge clk);
end
end
else if(!lc)
begin
for(i=0; i<6; i=i+1)
begin
dstrb <= #1 1'b1;
din = #1 ihuff[i];
@(posedge clk);
dstrb <= #1 1'b0;
repeat(1)@(posedge clk);
end
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address = 0x0001
// FDCT in, RLE out
task test_addr1;
begin
$display("********************************");
$display("Testing Address = 0x0001");
$display("********************************");
addr <= 4'h1;
dstrb <= #1 1'b1;
@(posedge clk);
dstrb <= #1 1'b0;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 cl[i] - 12'd128;
else din = #1 il[i] - 12'd128;
@(posedge clk);
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address = 0x0010
// FDCT in, QNR out
task test_addr2;
begin
$display("********************************");
$display("Testing Address = 0x0010");
$display("********************************");
addr <= 4'h2;
dstrb <= #1 1'b1;
@(posedge clk);
dstrb <= #1 1'b0;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 cl[i] - 12'd128;
else din = #1 il[i] - 12'd128;
@(posedge clk);
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address = 0x0011
// FDCT in, FDCT out
task test_addr3;
begin
$display("********************************");
$display("Testing Address = 0x0011");
$display("********************************");
addr <= 4'h3;
dstrb <= #1 1'b1;
@(posedge clk);
dstrb <= #1 1'b0;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 cl[i] - 12'd128;
else din = #1 il[i] - 12'd128;
@(posedge clk);
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address = 0x0101
// QNR in, RLE out
task test_addr5;
begin
$display("********************************");
$display("Testing Address = 0x0101");
$display("********************************");
addr <= 4'h5;
dstrb <= #1 1'b1;
@(posedge clk);
dstrb <= #1 1'b0;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 cqnr[i];
else din = #1 iqnr[i];
@(posedge clk);
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address = 0x0110
// QNR in, QNR out
task test_addr6;
begin
$display("********************************");
$display("Testing Address = 0x0110");
$display("********************************");
addr <= 4'h6;
dstrb <= #1 1'b1;
@(posedge clk);
dstrb <= #1 1'b0;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 cqnr[i];
else din = #1 iqnr[i];
@(posedge clk);
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
// Address 0x1001
// RLE in, RLE out
task test_addr9;
begin
$display("********************************");
$display("Testing Address = 0x1001");
$display("********************************");
addr <= 4'h9;
dstrb <= #1 1'b1;
for(i=0; i<64; i=i+1)
begin
if(lc) din = #1 crle[i];
else din = #1 irle[i];
@(posedge clk);
dstrb <= #1 1'b0;
end
repeat(150)@(posedge clk);
$display("Total Errors: %d",err);
err = 0;
cnt = 0;
end
endtask
endmodule
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