📄 top_tb_rev0.v
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`timescale 1ns / 10ps
module top_tb();
reg clk; // sys clock
reg rst; // asynch active-low rst
reg nce; // chip select
reg awe, are; // asynch read/write enable
reg [8:0] din; // Data in {LC,DATA}
//wire [10:0] dout; //{FIFO_EMPTY,EOB,LC,DATA}
reg [7:0] input_list [127:0]; //
reg en;
wire [10:0] data;
integer i;
////////////////////////////
wire [7:0] encdin,encdout;
reg [5:0] count;
////////////////////////////
assign data = en ? {2'b00,din} : 11'bz;
//
// Instantiate top level encoder
//
wire [11:0] fdct_dout;
wire [10:0] qnr_dout;
top_enc top_enc(
.clk(clk),
.rst(rst),
.nce(nce),
.awe(awe),
.are(are),
.data(data),
//Test inputs/outputs
.encdin(encdin),
.dstrb(dstrb),
.encdout(encdout),
.douten(douten),
.fdct_dout(fdct_dout),
.fdct_doe(fdct_doe),
.qnr_dout(qnr_dout),
.qnr_doe(qnr_doe)
// .din(din),
// .dout(dout)
);
always @ (posedge clk)
begin
if(dstrb)
begin
count <= count + 1;
$display("Data Input: %x",encdin);
end
else if(count != 6'h00)
begin
count <= count + 1;
$display("Data Input: %x",encdin);
end
end
always @ (posedge clk)
begin
if(douten)
$display("Data Output: %x",encdout);
end
always #20 clk <= ~clk;
initial
begin
#0 count <= 6'h00;
// Luminance Block
#0 input_list[00] <= 8'd70 - 8'd128;
#0 input_list[01] <= 8'd72 - 8'd128;
#0 input_list[02] <= 8'd70 - 8'd128;
#0 input_list[03] <= 8'd70 - 8'd128;
#0 input_list[04] <= 8'd72 - 8'd128;
#0 input_list[05] <= 8'd68 - 8'd128;
#0 input_list[06] <= 8'd68 - 8'd128;
#0 input_list[07] <= 8'd64 - 8'd128;
#0 input_list[08] <= 8'd103 - 8'd128;
#0 input_list[09] <= 8'd101 - 8'd128;
#0 input_list[10] <= 8'd103 - 8'd128;
#0 input_list[11] <= 8'd100 - 8'd128;
#0 input_list[12] <= 8'd99 - 8'd128;
#0 input_list[13] <= 8'd97 - 8'd128;
#0 input_list[14] <= 8'd94 - 8'd128;
#0 input_list[15] <= 8'd94 - 8'd128;
#0 input_list[16] <= 8'd132 - 8'd128;
#0 input_list[17] <= 8'd132 - 8'd128;
#0 input_list[18] <= 8'd132 - 8'd128;
#0 input_list[19] <= 8'd130 - 8'd128;
#0 input_list[20] <= 8'd129 - 8'd128;
#0 input_list[21] <= 8'd129 - 8'd128;
#0 input_list[22] <= 8'd125 - 8'd128;
#0 input_list[23] <= 8'd121 - 8'd128;
#0 input_list[24] <= 8'd157 - 8'd128;
#0 input_list[25] <= 8'd157 - 8'd128;
#0 input_list[26] <= 8'd155 - 8'd128;
#0 input_list[27] <= 8'd154 - 8'd128;
#0 input_list[28] <= 8'd153 - 8'd128;
#0 input_list[29] <= 8'd150 - 8'd128;
#0 input_list[30] <= 8'd148 - 8'd128;
#0 input_list[31] <= 8'd145 - 8'd128;
#0 input_list[32] <= 8'd168 - 8'd128;
#0 input_list[33] <= 8'd163 - 8'd128;
#0 input_list[34] <= 8'd164 - 8'd128;
#0 input_list[35] <= 8'd162 - 8'd128;
#0 input_list[36] <= 8'd163 - 8'd128;
#0 input_list[37] <= 8'd161 - 8'd128;
#0 input_list[38] <= 8'd161 - 8'd128;
#0 input_list[39] <= 8'd156 - 8'd128;
#0 input_list[40] <= 8'd172 - 8'd128;
#0 input_list[41] <= 8'd170 - 8'd128;
#0 input_list[42] <= 8'd165 - 8'd128;
#0 input_list[43] <= 8'd166 - 8'd128;
#0 input_list[44] <= 8'd163 - 8'd128;
#0 input_list[45] <= 8'd163 - 8'd128;
#0 input_list[46] <= 8'd162 - 8'd128;
#0 input_list[47] <= 8'd158 - 8'd128;
#0 input_list[48] <= 8'd174 - 8'd128;
#0 input_list[49] <= 8'd170 - 8'd128;
#0 input_list[50] <= 8'd167 - 8'd128;
#0 input_list[51] <= 8'd167 - 8'd128;
#0 input_list[52] <= 8'd164 - 8'd128;
#0 input_list[53] <= 8'd163 - 8'd128;
#0 input_list[54] <= 8'd164 - 8'd128;
#0 input_list[55] <= 8'd159 - 8'd128;
#0 input_list[56] <= 8'd174 - 8'd128;
#0 input_list[57] <= 8'd173 - 8'd128;
#0 input_list[58] <= 8'd170 - 8'd128;
#0 input_list[59] <= 8'd167 - 8'd128;
#0 input_list[60] <= 8'd167 - 8'd128;
#0 input_list[61] <= 8'd166 - 8'd128;
#0 input_list[62] <= 8'd166 - 8'd128;
#0 input_list[63] <= 8'd160 - 8'd128;
//Chrominance Block
#0 input_list[64] <= 8'd151;
#0 input_list[65] <= 8'd147;
#0 input_list[66] <= 8'd152;
#0 input_list[67] <= 8'd140;
#0 input_list[68] <= 8'd138;
#0 input_list[69] <= 8'd125;
#0 input_list[70] <= 8'd136;
#0 input_list[71] <= 8'd160;
#0 input_list[72] <= 8'd157;
#0 input_list[73] <= 8'd148;
#0 input_list[74] <= 8'd152;
#0 input_list[75] <= 8'd137;
#0 input_list[76] <= 8'd124;
#0 input_list[77] <= 8'd105;
#0 input_list[78] <= 8'd108;
#0 input_list[79] <= 8'd144;
#0 input_list[80] <= 8'd152;
#0 input_list[81] <= 8'd151;
#0 input_list[82] <= 8'd146;
#0 input_list[83] <= 8'd128;
#0 input_list[84] <= 8'd99;
#0 input_list[85] <= 8'd73;
#0 input_list[86] <= 8'd75;
#0 input_list[87] <= 8'd116;
#0 input_list[88] <= 8'd154;
#0 input_list[89] <= 8'd148;
#0 input_list[90] <= 8'd145;
#0 input_list[91] <= 8'd111;
#0 input_list[92] <= 8'd91;
#0 input_list[93] <= 8'd68;
#0 input_list[94] <= 8'd62;
#0 input_list[95] <= 8'd98;
#0 input_list[96] <= 8'd156;
#0 input_list[97] <= 8'd144;
#0 input_list[98] <= 8'd147;
#0 input_list[99] <= 8'd93;
#0 input_list[100] <= 8'd97;
#0 input_list[101] <= 8'd105;
#0 input_list[102] <= 8'd61;
#0 input_list[103] <= 8'd82;
#0 input_list[104] <= 8'd155;
#0 input_list[105] <= 8'd139;
#0 input_list[106] <= 8'd149;
#0 input_list[107] <= 8'd76;
#0 input_list[108] <= 8'd101;
#0 input_list[109] <= 8'd140;
#0 input_list[110] <= 8'd59;
#0 input_list[111] <= 8'd74;
#0 input_list[112] <= 8'd148;
#0 input_list[113] <= 8'd135;
#0 input_list[114] <= 8'd147;
#0 input_list[115] <= 8'd71;
#0 input_list[116] <= 8'd114;
#0 input_list[117] <= 8'd158;
#0 input_list[118] <= 8'd79;
#0 input_list[119] <= 8'd66;
#0 input_list[120] <= 8'd135;
#0 input_list[121] <= 8'd120;
#0 input_list[122] <= 8'd133;
#0 input_list[123] <= 8'd92;
#0 input_list[124] <= 8'd133;
#0 input_list[125] <= 8'd176;
#0 input_list[126] <= 8'd103;
#0 input_list[127] <= 8'd60;
#0 clk <= 1'b0;
#0 rst <= 1'b0;
#0 nce <= 1'b1;
#0 awe <= 1'b1;
#0 are <= 1'b1;
#0 din <= 9'h0;
#0 en <= 1'b1;
#17 rst <= 1'b1;
// wait awhile
repeat(20) @(posedge clk);
din <= 0;
@(posedge clk);
nce <= 1'b0;
awe <= 1'b0;
repeat(2)@(posedge clk);
nce <= 1'b1;
awe <= 1'b1;
for(i=0; i<64; i=i+1)
begin
din <= {1'b0,input_list[i]};
@(posedge clk);
nce <= 1'b0;
awe <= 1'b0;
repeat(2)@(posedge clk);
nce <= 1'b1;
awe <= 1'b1;
repeat(2)@(posedge clk);
end
en <= 1'b0;
repeat(10)@(posedge clk);
// while(data[9] != 1'b1)
while(1)
begin
nce <= 1'b0;
are <= 1'b0;
while(data[10])
begin
@(posedge clk);
nce <= 1'b1;
are <= 1'b1;
@(posedge clk)
nce <= 1'b0;
are <= 1'b0;
end
repeat(2)@(posedge clk);
$display("Dout = %x lc = %x eob = %x",data[7:0],data[8],data[9]);
nce <= 1'b1;
are <= 1'b1;
repeat(2)@(posedge clk);
end
$display("END OF TESTBENCH");
/*
for(i=64; i<128; i=i+1)
begin
din <= {1'b1,input_list[i]-8'd128};
nce <= 1'b0;
awe <= 1'b0;
repeat(2)@(posedge clk);
nce <= 1'b1;
awe <= 1'b1;
repeat(2)@(posedge clk);
end
*/
end
endmodule
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