📄 top_tb_rev2.v
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`timescale 1ns / 1ps
module top_tb();
parameter verbose = 1;
parameter timing = 1;
// Input Registers
reg clk, clkdiv;
reg rst;
reg nce;
reg awe;
reg are;
reg [5:0] addr;
reg lc;
reg [12:0] din;
reg [11:0] il [63:0];
reg [11:0] iqnr [63:0];
reg [11:0] irle [63:0];
reg [11:0] ihuff [5:0];
reg toggle;
reg [3:0] inaddr;
integer i;
reg stop;
reg [24:0] temp;
wire [24:0] data;
assign data = (~nce & ~awe) ? {12'h0,din} : 25'bz;
// Generate Clock
always # 20 clk <= ~clk;
// Instantiate DUT
top_enc top_enc(
.clkin(clk),
.rst(rst),
.nce(nce),
.are(are),
.awe(awe),
.data(data),
.addr(addr),
.clkout(clkout)
);
// Initialize Value
initial
begin
#0 il[00] <= 12'd70;
#0 il[01] <= 12'd72;
#0 il[02] <= 12'd70;
#0 il[03] <= 12'd70;
#0 il[04] <= 12'd72;
#0 il[05] <= 12'd68;
#0 il[06] <= 12'd68;
#0 il[07] <= 12'd64;
#0 il[08] <= 12'd103;
#0 il[09] <= 12'd101;
#0 il[10] <= 12'd103;
#0 il[11] <= 12'd100;
#0 il[12] <= 12'd99;
#0 il[13] <= 12'd97;
#0 il[14] <= 12'd94;
#0 il[15] <= 12'd94;
#0 il[16] <= 12'd132;
#0 il[17] <= 12'd132;
#0 il[18] <= 12'd132;
#0 il[19] <= 12'd130;
#0 il[20] <= 12'd129;
#0 il[21] <= 12'd129;
#0 il[22] <= 12'd125;
#0 il[23] <= 12'd121;
#0 il[24] <= 12'd157;
#0 il[25] <= 12'd157;
#0 il[26] <= 12'd155;
#0 il[27] <= 12'd154;
#0 il[28] <= 12'd153;
#0 il[29] <= 12'd150;
#0 il[30] <= 12'd148;
#0 il[31] <= 12'd145;
#0 il[32] <= 12'd168;
#0 il[33] <= 12'd163;
#0 il[34] <= 12'd164;
#0 il[35] <= 12'd162;
#0 il[36] <= 12'd163;
#0 il[37] <= 12'd161;
#0 il[38] <= 12'd161;
#0 il[39] <= 12'd156;
#0 il[40] <= 12'd172;
#0 il[41] <= 12'd170;
#0 il[42] <= 12'd165;
#0 il[43] <= 12'd166;
#0 il[44] <= 12'd163;
#0 il[45] <= 12'd163;
#0 il[46] <= 12'd162;
#0 il[47] <= 12'd158;
#0 il[48] <= 12'd174;
#0 il[49] <= 12'd170;
#0 il[50] <= 12'd167;
#0 il[51] <= 12'd167;
#0 il[52] <= 12'd164;
#0 il[53] <= 12'd163;
#0 il[54] <= 12'd164;
#0 il[55] <= 12'd159;
#0 il[56] <= 12'd174;
#0 il[57] <= 12'd173;
#0 il[58] <= 12'd170;
#0 il[59] <= 12'd167;
#0 il[60] <= 12'd167;
#0 il[61] <= 12'd166;
#0 il[62] <= 12'd166;
#0 il[63] <= 12'd160;
#0 iqnr[0] <= 12'h0ac;
#0 iqnr[1] <= 12'h034;
#0 iqnr[2] <= 12'he12;
#0 iqnr[3] <= 12'hf16;
#0 iqnr[4] <= 12'hff8;
#0 iqnr[5] <= 12'hffa;
#0 iqnr[6] <= 12'h00c;
#0 iqnr[7] <= 12'hff6;
#0 iqnr[8] <= 12'hffd;
#0 iqnr[9] <= 12'hfb0;
#0 iqnr[10] <= 12'hff2;
#0 iqnr[11] <= 12'hffb;
#0 iqnr[12] <= 12'h000;
#0 iqnr[13] <= 12'hffa;
#0 iqnr[14] <= 12'hffb;
#0 iqnr[15] <= 12'h004;
#0 iqnr[16] <= 12'h000;
#0 iqnr[17] <= 12'hffe;
#0 iqnr[18] <= 12'h002;
#0 iqnr[19] <= 12'hffb;
#0 iqnr[20] <= 12'hff4;
#0 iqnr[21] <= 12'hff7;
#0 iqnr[22] <= 12'h001;
#0 iqnr[23] <= 12'hffd;
#0 iqnr[24] <= 12'h001;
#0 iqnr[25] <= 12'hffe;
#0 iqnr[26] <= 12'hffa;
#0 iqnr[27] <= 12'hffc;
#0 iqnr[28] <= 12'h002;
#0 iqnr[29] <= 12'h002;
#0 iqnr[30] <= 12'hffe;
#0 iqnr[31] <= 12'h003;
#0 iqnr[32] <= 12'h001;
#0 iqnr[33] <= 12'hffe;
#0 iqnr[34] <= 12'hffe;
#0 iqnr[35] <= 12'hff9;
#0 iqnr[36] <= 12'hffa;
#0 iqnr[37] <= 12'hffe;
#0 iqnr[38] <= 12'hfff;
#0 iqnr[39] <= 12'hffe;
#0 iqnr[40] <= 12'h001;
#0 iqnr[41] <= 12'hffd;
#0 iqnr[42] <= 12'h001;
#0 iqnr[43] <= 12'h000;
#0 iqnr[44] <= 12'hffc;
#0 iqnr[45] <= 12'hffe;
#0 iqnr[46] <= 12'hfff;
#0 iqnr[47] <= 12'h002;
#0 iqnr[48] <= 12'hffe;
#0 iqnr[49] <= 12'h002;
#0 iqnr[50] <= 12'hffc;
#0 iqnr[51] <= 12'hfff;
#0 iqnr[52] <= 12'hffd;
#0 iqnr[53] <= 12'hfff;
#0 iqnr[54] <= 12'h003;
#0 iqnr[55] <= 12'hffb;
#0 iqnr[56] <= 12'hffd;
#0 iqnr[57] <= 12'hffe;
#0 iqnr[58] <= 12'h002;
#0 iqnr[59] <= 12'hffd;
#0 iqnr[60] <= 12'hffd;
#0 iqnr[61] <= 12'hffd;
#0 iqnr[62] <= 12'h000;
#0 iqnr[63] <= 12'h002;
#0 irle[0] <= 12'h005;
#0 irle[1] <= 12'h002;
#0 irle[2] <= 12'hfeb;
#0 irle[3] <= 12'hff8;
#0 irle[4] <= 12'h000;
#0 irle[5] <= 12'h000;
#0 irle[6] <= 12'h000;
#0 irle[7] <= 12'h000;
#0 irle[8] <= 12'h000;
#0 irle[9] <= 12'hffd;
#0 irle[10] <= 12'h000;
#0 irle[11] <= 12'h000;
#0 irle[12] <= 12'h000;
#0 irle[13] <= 12'h000;
#0 irle[14] <= 12'h000;
#0 irle[15] <= 12'h000;
#0 irle[16] <= 12'h000;
#0 irle[17] <= 12'h000;
#0 irle[18] <= 12'h000;
#0 irle[19] <= 12'h000;
#0 irle[20] <= 12'h000;
#0 irle[21] <= 12'h000;
#0 irle[22] <= 12'h000;
#0 irle[23] <= 12'h000;
#0 irle[24] <= 12'h000;
#0 irle[25] <= 12'h000;
#0 irle[26] <= 12'h000;
#0 irle[27] <= 12'h000;
#0 irle[28] <= 12'h000;
#0 irle[29] <= 12'h000;
#0 irle[30] <= 12'h000;
#0 irle[31] <= 12'h000;
#0 irle[32] <= 12'h000;
#0 irle[33] <= 12'h000;
#0 irle[34] <= 12'h000;
#0 irle[35] <= 12'h000;
#0 irle[36] <= 12'h000;
#0 irle[37] <= 12'h000;
#0 irle[38] <= 12'h000;
#0 irle[39] <= 12'h000;
#0 irle[40] <= 12'h000;
#0 irle[41] <= 12'h000;
#0 irle[42] <= 12'h000;
#0 irle[43] <= 12'h000;
#0 irle[44] <= 12'h000;
#0 irle[45] <= 12'h000;
#0 irle[46] <= 12'h000;
#0 irle[47] <= 12'h000;
#0 irle[48] <= 12'h000;
#0 irle[49] <= 12'h000;
#0 irle[50] <= 12'h000;
#0 irle[51] <= 12'h000;
#0 irle[52] <= 12'h000;
#0 irle[53] <= 12'h000;
#0 irle[54] <= 12'h000;
#0 irle[55] <= 12'h000;
#0 irle[56] <= 12'h000;
#0 irle[57] <= 12'h000;
#0 irle[58] <= 12'h000;
#0 irle[59] <= 12'h000;
#0 irle[60] <= 12'h000;
#0 irle[61] <= 12'h000;
#0 irle[62] <= 12'h000;
#0 irle[63] <= 12'h000;
#0 ihuff[0] <= 12'h003;
#0 ihuff[1] <= 12'h002;
#0 ihuff[2] <= 12'h005;
#0 ihuff[3] <= 12'h004;
#0 ihuff[4] <= 12'h052;
#0 ihuff[5] <= 12'h000;
#0 clk <= 1'b0;
#0 clkdiv <= 1'b1;
#0 rst <= 1'b0;
#0 nce <= 1'b1;
#0 are <= 1'b1;
#0 awe <= 1'b1;
#0 din <= 12'h0;
#0 addr<= 6'h0;
#0 lc <= 1'b0;
#0 stop <= 1'b0;
#0 toggle <= 1'b1;
#0 inaddr <= 4'h0;
#0 temp <= 25'h0;
#500 rst <= 1'b1;
// Wait awhile
repeat(150)@(posedge clk);
// Just for timing sims
if(timing)
begin
nce <= 1'b0;
din <= 12'h0;
addr <= 6'hf;
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
end
// Tests Luminance
test_addr0; // fdct -> huff
test_addr4; // qnr -> huff
test_addr8; // rle -> huff
test_addrC; // huff -> huff
$stop;
end
task test_addr0;
begin
$display("********TEST ADDR0********");
// Set Control Reg
addr <= 6'h10;
inaddr <= 4'h0;
nce <= 1'b0;
#10 din <= {7'h0, clkdiv, lc, inaddr};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(10)@(posedge clk);
read_status;
repeat(10)@(posedge clk);
// Write Data
addr <= 6'h00;
for(i=0; i<64; i=i+1)
begin
nce <= 1'b0;
din <= {lc,(il[i]-12'd128)};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(2)@(posedge clk);
end
read_data;
repeat(100)@(posedge clk);
end
endtask
task test_addr4;
begin
$display("********TEST ADDR4********");
// Set Control Reg
addr <= 6'h10;
inaddr <= 4'h4;
nce <= 1'b0;
#10 din <= {7'h0, clkdiv, lc, inaddr};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(10)@(posedge clk);
read_status;
repeat(10)@(posedge clk);
// Write Data
addr <= 6'h00;
for(i=0; i<64; i=i+1)
begin
nce <= 1'b0;
din <= {lc,iqnr[i]};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(2)@(posedge clk);
end
read_data;
repeat(100)@(posedge clk);
end
endtask
task test_addr8;
begin
$display("*********TEST ADDR8********");
// Set Control Reg
addr <= 6'h10;
inaddr <= 4'h8;
nce <= 1'b0;
#10 din <= {7'h0, clkdiv, lc, inaddr};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(10)@(posedge clk);
read_status;
repeat(10)@(posedge clk);
// Write Data
addr <= 6'h00;
for(i=0; i<64; i=i+1)
begin
nce <= 1'b0;
din <= {lc,irle[i]};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(2)@(posedge clk);
end
read_data;
repeat(100)@(posedge clk);
end
endtask
task test_addrC;
begin
$display("*********TEST ADDRC********");
// Set Control Reg
addr <= 6'h10;
inaddr <= 4'hC;
nce <= 1'b0;
#10 din <= {7'h0, clkdiv, lc, inaddr};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(10)@(posedge clk);
read_status;
repeat(10)@(posedge clk);
// Write Data
addr <= 6'h00;
for(i=0; i<6; i=i+1)
begin
nce <= 1'b0;
din <= {lc,ihuff[i]};
#10 awe <= 1'b0;
#50 awe <= 1'b1;
nce <= 1'b1;
repeat(2)@(posedge clk);
end
read_data;
repeat(100)@(posedge clk);
end
endtask
task read_status;
begin
addr <= 6'h20;
nce <= 1'b0;
#10 are <= 1'b0;
#10 $display("Status = %x",data&13'h1FFF);
#30 are <= 1'b1;
nce <= 1'b1;
repeat(100)@(posedge clk);
addr <= 6'h00;
end
endtask
task read_data;
begin
while(!stop)
begin
nce <= 1'b0;
#10 are <= 1'b0;
if(addr[1:0] == 2'b00)
begin
#40 stop <= temp != data ? data[23] & data[21] : 1'b0;
if(toggle != data[24])
begin
temp <= data;
if(data[22] && data[21] && temp != data)
begin
$display("Amp = %x",data[19:8]);
$display("Huff = %x",data[7:0]);
toggle <= toggle==data[24] ? toggle : data[24];
end
else if(data[22] || data[21])
begin
if(data[22])
$display("Amp = %x",data[19:8]);
if(data[21])
$display("Huff = %x",data[7:0]);
toggle <= toggle==data[24] ? toggle : data[24];
end
end
end
#50 are <= 1'b1;
#10 nce <= 1'b1;
end
stop <= 1'b0;
end
endtask
endmodule
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