top_enc_rev1.v

Verilog jpec coder encoder source code

`timescale 1ns / 10ps

module top_enc(clk, rst, nce, awe, are, data, addr);

	//
	// Inputs & Outputs
	//
	input clk;		// 25MHz Clock
	input rst;		// Async Active-Low Reset
	input nce;		// Chip Enable (Ative-Low)
	input awe;		// Async Write Enable
	input are;		// Async Read Enable
	input [3:0] addr;	// Address Input
	
	inout [22:0] data;	// Data Output {doe,EOB,LC,DATA}
	
	wire [12:0] din;
	reg dstrb, rd_en;
	//
	// Luminance / Chrominance 
	//
	reg lc;
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
			lc <= 1'b0;
		else
			lc <= din[12];
	end
	
	// 
	// Wires
	// 
	
	wire [22:0] dout;		// Output Data
	assign data = (~are & ~nce) ? dout : 23'bz;

	//
	// State Machine for Data Input to Encoder
	//
	reg state;
	reg [5:0] cnt, icnt;
	wire inempty;	//input fifo empty
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			dstrb <= 1'b0;
			state <= 1'b0;
			cnt <= 6'h0;
			rd_en <= 1'b0;
			icnt <= 6'h0;
		end
		else if(!(&icnt) && !nce && !awe && !(&addr[3:2]))
		begin
			icnt <= icnt + 1;
			rd_en <= 1'b0;
		end
		else if(&icnt && !addr[3]) // Data Strobe, then input 64 values (DCT,QNR)
		begin
			case(state)
				1'b0:
				begin
					dstrb <= 1'b1;
					state <= ~state;
					cnt <= 6'h0;
					rd_en <= 1'b1;
				end	
				1'b1:
				begin
					dstrb <= 1'b0;
					cnt <= cnt + 1;
					state <= &cnt ? ~state : state;
					icnt <= &cnt ? 6'h0 : icnt;
					rd_en <= &cnt ? 1'b0 : 1'b1;
				end
			endcase
		end
			
		else if(&icnt && addr[3] && !addr[2]) // Data strobe at same time as data
		begin
			case(state)
				1'b0:
				begin
					dstrb <= 1'b0;
					state <= ~state;
					cnt <= 6'h0;
					rd_en <= 1'b1;
				end	
				1'b1:
				begin
					dstrb <= |cnt ? 1'b0 : 1'b1;
					cnt <= cnt + 1;
					state <= &cnt ? ~state : state;
					icnt <= &cnt ? 6'h0 : icnt;
					rd_en <= &cnt ? 1'b0 : 1'b1;
				end
			endcase
		end

		else if(&addr[3:2])
		begin
			case(state)
				1'b0:
				begin
						rd_en <= ~inempty ? 1'b1 : 1'b0;
						dstrb <= 1'b0;
						state <= ~inempty ? ~state : state;
				end
				
				1'b1:
				begin
						rd_en <= 1'b0;
						dstrb <= 1'b1;
						state <= ~state;
				end
			endcase	
		end
	end
	
	// 
	// Instantiate Input FIFO
	//
	in_fifo in_fifo(
		.din(data[12:0]), //{LC,DATA}
		.wr_en(~nce),
		.wr_clk(~awe && ~nce),
		.rd_en(rd_en),	// Read Enable from state machine
		.rd_clk(clk),
		.ainit(~rst), 	// FIFO reset active high
		.dout(din), 
		.full(),
		.empty(inempty)
	);

	//
	// Instantiate JPEG Encoder
	//
	wire [19:0] do_enc;	//Output of encoder
	jpeg_encoder enc(
		.clk(clk),
		.rst(rst),
		.lc(din[12]),
		.dstrb(dstrb),
		.din(din[11:0]),
		.addr(addr),
		.eob(eob),
		.doe(doe),
		.dout(do_enc)
	);

	// 
	// Instantiate Output FIFO
	// 
	out_fifo out_fifo(
		.din({doe,eob,lc,do_enc}), //22-bit
		.wr_en(doe),
		.wr_clk(~clk),
		.rd_en(~nce),
		.rd_clk(~are && ~nce),
		.ainit(~rst),
		.dout(dout[22:0]),	//22-bit
		.full(),
		.empty()
	);

		

endmodule