top_enc_rev2.v

Verilog jpec coder encoder source code

`timescale 1ns / 10ps

module top_enc(clk, rst, nce, awe, are, data, addr);

	//
	// Inputs & Outputs
	//
	input clk;		// 25MHz Clock
	input rst;		// Async Active-Low Reset
	input nce;		// Chip Enable (Ative-Low)
	input awe;		// Async Write Enable
	input are;		// Async Read Enable
	input [5:0] addr;	// Address Input
	
	inout [22:0] data;	// Data Output {doe,EOB,LC,DATA}
	
	wire [12:0] din;
	reg dstrb, rd_en;
	reg [4:0] control;	// [LC,ADDR3,ADDR2,ADDR1,ADDR0]
	reg update;	// Can only update control when set to 1

	//in_full, in_empty, out_full, out_empty, lc,
	//dct_comp, qnr_comp, rle_comp, huff_comp,
	//dctin,dctout,qnrin,qnrout,rlein,rleout,huffin,huffout]
	reg [16:0] status; 
	wire eob;
	// 
	// Control Register - Address 16
	//

	always @ (posedge clk or negedge rst)
	begin
		if(~rst)
		begin
			control <= 5'h0;
			update <= 1'b1;
		end
		else if(eob) // can only update control after block
			update <= 1'b1;
		else if(addr == 6'h10 && update)
		begin
			control <= data[4:0]; //{LC,ADDR[3:0]}
			update <= 1'b0;
		end
	end
	
	// 
	// Status Register - Address 32
	//
	wire in_full, in_empty, out_full, out_empty;
	wire [11:0] encstat;
	always @ (posedge clk or negedge rst)
	begin
		if(~rst)
			status <= 13'h0;
		else 
			status <= {control[4],in_full,in_empty,out_full,out_empty,encstat};			
	end
	
	// 
	// Wires
	// 
	
	wire [22:0] dout;		// Output Data
	assign data = (~are & ~nce & addr[5]) ? status : 
			                (~are & ~nce) ? dout : 23'bz;

	//
	// State Machine for Data Input to Encoder
	//
	reg state;
	reg [5:0] cnt, icnt;
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			dstrb <= 1'b0;
			state <= 1'b0;
			cnt <= 6'h0;
			rd_en <= 1'b0;
			icnt <= 6'h0;
		end
		else if(!(&icnt) && !nce && !awe && !(&control[3:2]) && !(|addr[5:4]))
		begin
			icnt <= icnt + 1;
			rd_en <= 1'b0;
		end
		else if(&icnt && !control[3] && !(|addr[5:4])) // Data Strobe, then input 64 values (DCT,QNR)
		begin
			case(state)
				1'b0:
				begin
					dstrb <= 1'b1;
					state <= ~state;
					cnt <= 6'h0;
					rd_en <= 1'b1;
				end	
				1'b1:
				begin
					dstrb <= 1'b0;
					cnt <= cnt + 1;
					state <= &cnt ? ~state : state;
					icnt <= &cnt ? 6'h0 : icnt;
					rd_en <= &cnt ? 1'b0 : 1'b1;
				end
			endcase
		end
			
		else if(&icnt && control[3] && !control[2] && !(|addr[5:4])) // Data strobe at same time as data
		begin
			case(state)
				1'b0:
				begin
					dstrb <= 1'b0;
					state <= ~state;
					cnt <= 6'h0;
					rd_en <= 1'b1;
				end	
				1'b1:
				begin
					dstrb <= |cnt ? 1'b0 : 1'b1;
					cnt <= cnt + 1;
					state <= &cnt ? ~state : state;
					icnt <= &cnt ? 6'h0 : icnt;
					rd_en <= &cnt ? 1'b0 : 1'b1;
				end
			endcase
		end

		else if(&control[3:2] && !(|addr[5:4]))
		begin
			case(state)
				1'b0:
				begin
						rd_en <= ~in_empty ? 1'b1 : 1'b0;
						dstrb <= 1'b0;
						state <= ~in_empty ? ~state : state;
				end
				
				1'b1:
				begin
						rd_en <= 1'b0;
						dstrb <= 1'b1;
						state <= ~state;
				end
			endcase	
		end
	end
	
	// 
	// Instantiate Input FIFO
	//
	in_fifo in_fifo(
		.din(data[12:0]), //{LC,DATA}
		.wr_en(~nce),
		.wr_clk((~awe && ~nce) && !(|addr[5:4])),
		.rd_en(rd_en),	// Read Enable from state machine
		.rd_clk(clk),
		.ainit(~rst), 	// FIFO reset active high
		.dout(din), 
		.full(in_full),
		.empty(in_empty)
	);

	//
	// Instantiate JPEG Encoder
	//
	wire [19:0] do_enc;	//Output of encoder
	jpeg_encoder enc(
		.clk(clk),
		.rst(rst),
		.lc(control[4]),
		.dstrb(dstrb),
		.din(din[11:0]),
		.addr(control[3:0]),
		.eob(eob),
		.doe(doe),
		.dout(do_enc),
		.encstat(encstat)
	);

	// 
	// Instantiate Output FIFO
	// 
	out_fifo out_fifo(
		.din({doe,eob,control[4],do_enc}), //22-bit
		.wr_en(doe),
		.wr_clk(~clk),
		.rd_en(~nce),
		.rd_clk(~are && ~nce && !(|addr[5:4])),
		.ainit(~rst),
		.dout(dout[22:0]),	//22-bit
		.full(out_full),
		.empty(out_empty)
	);

		

endmodule