top_enc_rev0.v

Verilog jpec coder encoder source code

`timescale 1ns / 10ps

module top_enc(clk, rst, nce, awe, are,data,encdin,dstrb,encdout,douten,fdct_dout,fdct_doe,qnr_dout,qnr_doe);/* din, dout);*/

	//
	// Inputs & Outputs
	//
	input clk;			// 25MHz Clock
	input rst;			// Asynch Active-Low Reset
	input nce;			// FPGA address space chip select
	input awe;			// Asynch Write Enable
	input are;			// Asynch Read Enable
	//input [8:0] din;	// Data input {LC,DATA}

	//output [10:0] dout;	// Data Output {FIFO_EMPTY,LC,EOB,DATA}
	inout [10:0] data;

	//test outputs***********
	output [7:0] encdin;
	output dstrb;
	output [7:0] encdout;
	output douten;
	output [11:0] fdct_dout;
	output [10:0] qnr_dout;
	output fdct_doe, qnr_doe;
	//***********************
	
	//
	// Registers
	//
	reg dstrb;
	reg [1:0] state;
	reg read;
	reg curr_lc, next_lc;
	reg [5:0] count;
	reg [5:0] input_count;
	reg deob;
	
	//
	// Wires
	//
	wire enc_eob;
	wire wr_clk, rd_clk;
	wire [8:0] input_fifo;
	wire [9:0] enc_dout; //{eob,lc,data}
	wire [10:0] dout;
	
	//test**************************
	wire [7:0] encdin;
	wire [7:0] encdout;
	assign encdin = input_fifo[7:0];
	assign encdout = enc_dout[7:0];
	//*******************************
	
	assign wr_clk = ~nce & ~awe;
	assign rd_clk = nce & are;
	
	//
	// Save lc info that is being processed
	// ? This may not be necessary ?
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			curr_lc	<= #1 1'b0;
			next_lc <= #1 1'b0;
		end
		else if(dstrb)
		begin
			curr_lc	<= #1 input_fifo[8];
			next_lc <= #1 curr_lc;
		end
	end

	// 
	// Instantiate Input FIFO
	//
	in_fifo in_fifo(
		.din(data[8:0]),		// 9-bit
		.wr_en(1'b1),
		.wr_clk(wr_clk),
		.rd_en(read),	// Read in data when clock not empty
		.rd_clk(clk), 	// 25 MHZ Clock
		.ainit(!rst),	// FIFO is active high reset
		.dout(input_fifo), // 9-bit {lc,data}
		.full(full),
		.empty(empty)
	);
	
	//
	// count input to signal block is ready
	//
	always @ (posedge wr_clk or negedge rst)
	begin
		if(!rst)
			input_count <= #1 6'h00;
		else
			input_count <= #1 input_count + 1;
	end	

	//
	// dstrb to dct unit should happen once per block
	// exactly one clock cycle prior to input data stream
	//
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			dstrb	<= #1 1'b0;
			state	<= #1 2'b00;
			count	<= #1 6'h00;
		end
		else
		begin
			case(state)
				2'b00: // When not empty data strobe
				begin
					count	<= #1 6'h00;
					if(&input_count)
					begin
						dstrb	<= #1 1'b0;
						state	<= #1 2'b11;
						read	<= #1 1'b1;
					end
					else
					begin	
						dstrb	<= #1 1'b0;
						read	<= #1 1'b0;
					end
				end
				2'b11:
				begin
					dstrb	<= #1 1'b1;
					state 	<= #1 2'b01;
				end
				2'b01: // Release data strobe, and read data
				begin
					dstrb	<= #1 1'b0;
					count	<= #1 count + 1;
					state	<= #1 &count ? 2'b00 : 2'b01;
					read 	<= #1 &count ? 1'b0 : 1'b1;
				end
					
			endcase
		end
	end
	
	//
	// Instantiate JPEG Encoder
	//
	wire [11:0] fdct_dout;
	wire [10:0] qnr_dout;
	jpeg_encoder enc(
		.clk(clk),
		.ena(1'b1),
		.rst(rst),
		.dstrb(dstrb),
		.lc(input_fifo[8]),	
		.din(input_fifo[7:0]),
		.dout(enc_dout[7:0]), // 8-bit
		.douten(douten),
		.eob(enc_eob)
		//TEST OUTPUTS
		,.fdct_dout(fdct_dout),
		.fdct_doe(fdct_doe),
		.qnr_dout(qnr_dout),
		.qnr_doe(qnr_doe)
	);
	
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
			deob <= #1 1'b0;
		else
			deob <= #1 enc_eob;
	end
			
	assign enc_dout[9] = deob;
	assign enc_dout[8] = next_lc;

	//
	// Instantiate Output FIFO
	//
	out_fifo	out_fifo(
			.din(enc_dout),
			.wr_en(douten),
			.wr_clk(clk),
			.rd_en(1'b1),
			.rd_clk(rd_clk),
			.ainit(!rst),
			.dout(dout[9:0]),
			.full(),
			.empty(dout[10])
	);
			
	assign data = (!nce & !are) ? dout : 11'bz;
endmodule