jpeg_encoder_rev0.v

Verilog jpec coder encoder source code

// Top Level JPEG Encoder
// DCT --> Zigzag --> QnR --> RLE --> Huffman

`timescale 1ns / 10ps
module jpeg_encoder(clk, ena, rst, dstrb, din, lc, dout, douten, eob
	/*TEST OUTPUTS*/
	,fdct_dout,fdct_doe,qnr_dout,qnr_doe);

	//
	// Parameters
	//
	parameter coef_width = 13;
	parameter di_width = 8;
	
	//
	// Inputs & Outputs
	//
	input clk;			// system clock
   	input ena;			// clock enable
	input rst;			// active low asynchronous reset
	input dstrb;		// data strobe. 1 clkc before block start
	input lc;			// luminance block (0), chrominance block (1)
	input [7:0] din;	// data input (block)

	output [7:0] dout;	// data output (huffman codewords)
	output douten;		// data output enable
	output eob;
	
	//TEsT OUTPUTS******************************************
	output [11:0] fdct_dout;
	output fdct_doe;

	output [10:0] qnr_dout;
	output qnr_doe;
	
	//******************************************************
	
	//TESTING
	//output [10:0] qnr_dout;
	//output qnr_doe;
	
	// 
	// Registers
	//
	
	// dct
	reg [11:0] dfdct_dout;	// DCT data output delayed 1 clock
	
	// qnr
	reg [7:0] dqnt_val;			// Quantization Value delayed 1 clock
	reg dqnr_doe, ddqnr_doe;	// QNR Data Out Enable delayed 1 clock/2 clock
	
	//
	// Wires
	//
	
	// outputs
	wire [7:0] dout;
	wire douten;
	
	// fdct
	wire [11:0] fdct_dout;	// DCT data output
	wire fdct_doe;

	// qnr
	wire [5:0] qnt_cnt;
	wire [10:0] qnr_dout;
	wire qnr_doe;
	
	// quantization tables
	wire [7:0] lum, chr, qnt_val;
	
	// rle
	wire [3:0] size, rlen; 		// size and run length
	wire [11:0] amp;			// amplitude
	wire rle_doe, bstart;		// data out enable / block start
	
	// huffman
	wire [1:0] tablesel;
	
	// 
	// Instantiate DCT module
	//
	fdct #(coef_width, di_width, 12)
	fdct(
		// inputs
		.clk(clk),
		.ena(ena),
		.rst(rst),
		.dstrb(dstrb),
		.din(din),	// 8-bits
		// outputs
		.dout(fdct_dout),
		.douten(fdct_doe)
	);
	
	//
	// delay dct data output by 1 clock cycle
	//
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
			dfdct_dout	<= #1 12'h0;
		else if(ena)
			dfdct_dout	<= #1 fdct_dout;
	end
	
	//
	// Instantiate Quantization Matrix for Lum & Chr
	//
	
	qlum qlum(
		.qnt_val(lum),
		.qnt_cnt(qnt_cnt)
	);

	qchr qchr(
		.qnt_val(chr),
		.qnt_cnt(qnt_cnt)
	);
	
	assign qnt_val = lc ? chr : lum;
	
	// Delay Quantization Value by 1 clock
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
			dqnt_val <= #1 8'b0;
		else if(ena)
			dqnt_val <= #1 qnt_val;
	end
	
	// 
	// Instantiate Quantization and Rounding Module
	//
	jpeg_qnr qnr(
		// Inputs
		.clk(clk),
		.ena(ena),
		.rst(rst),
		.dstrb(fdct_doe),
		.din(fdct_dout),	// 12-bit
		.qnt_val(qnt_val),	// 8-bit
		// Outputs
		.qnt_cnt(qnt_cnt),	// 6-bit
		.dout(qnr_dout),	// 11-bit
		.douten(qnr_doe),
		// Test Interface Outputs
		.div0(),
		.ovf(),
		.iq(),
		.rq(),
		.s()
	);

	// Delay output enable by 2 clocks
	always @ (posedge clk or negedge rst)
	begin
		if(!rst)
		begin
			dqnr_doe	<= #1 1'b0;
			ddqnr_doe	<= #1 1'b0;
		end
		else if(ena)
		begin
			dqnr_doe	<= #1 qnr_doe;
			ddqnr_doe	<= #1 dqnr_doe;
		end
	end

	//
	// Instantiate Run Length Encoder
	//
	jpeg_rle rle(
		// Inputs
		.clk(clk),
		.rst(rst),
		.ena(ena),
		.dstrb(dqnr_doe),
		.din({qnr_dout[10],qnr_dout}),
		// Outputs
		.size(size),
		.rlen(rlen),
		.amp(amp),
		.douten(rle_doe),
		.bstart(bstart)
	);

	//
	// Instantiate Huffman Tables
	//
	huffman_enc huff_enc(
		// Inputs
		.clk(clk),
		.rst(rst),
		.tablesel(tablesel),
		.di({rlen,size}),
		.die(rle_doe),
		// Outputs
		.do(dout),
		.doe(douten),
		.busy(),
		.eob(eob)
	);
		
	// table select
	assign tablesel[1] = bstart ? 1'b0 : 1'b1;
	assign tablesel[0] = lc;
		
endmodule