tb_div_uu_noreset.v

Verilog jpec coder encoder source code

`timescale 1ns / 10ps

module uu_tb();

	// Parameters
//  	parameter z_width = 12;
//  	parameter d_width = z_width/2;
//  	parameter z_width = 14;
//  	parameter d_width = 7;
//  	parameter pipeline = 8;
    	parameter z_width   = 24;
	parameter d_width   = z_width / 2;    
    	parameter pipeline  = 14;
    	parameter show_div0 = 0;
    	parameter show_ovf  = 1;
	parameter show_res  = 0;
        parameter test_ovf  = 0;
	
	// Inputs
    	reg clk;
    	reg [z_width-1:0] zi;
    	reg [d_width-1:0] di;


	// Outputs
    	wire [d_width-1:0] q;
    	wire [d_width-1:0] s;
    	wire div0;
    	wire ovf;

	// Internal Wires
    	integer z, d, n, sr, qr;
    	integer dz [pipeline-1:0];
    	integer dd [pipeline-1:0];
	integer count, err_cnt;
   	reg [d_width:0] sc, qc;
    
	//
	// hookup division unit
	//
	//
	//// Instantiate the UUT
    	div_uu  #(z_width) uut (
          .clk(clk), 	//system clock
          .ena(1'b1),   //clock enable
          .z(zi), 	//dividend
          .d(di), 	//divisor
          .q(q),	//quotient
          .s(s),	//remainder
          .div0(div0),	//divide by zero indicator
          .ovf(ovf)	//overflow indicator
	);

	always #2.5 clk <= ~clk;

	always@(posedge clk)
	  for(n=1; n<=pipeline-1; n=n+1)
	  begin
	    dz[n] <= #1 dz[n-1];
	    dd[n] <= #1 dd[n-1];
	  end

	initial
	begin
	    $display("*");
	    $display("* Starting testbench");
	    $display("*");
	    
	#0  err_cnt <= 0;
	#0  clk <= 0;		// start with low-level clock
	    count <= 0;
		
	    // wait a while
	    @(posedge clk);

	    // present data
//	    for(z=0; z < 1<<z_width; z=z+1)
//	    for(d=1; d < 1<<d_width; d=d+1)
	    for(z=0; z < 1<<12; z=z+1)
	    for(d=1; d < 1<<8; d=d+1) 
	    begin
	      zi <= z;
	      di <= d;

	      dz[0] <= z;
	      dd[0] <= d;

	      qr = count > z_width-3 ? dd[pipeline-1] == 0 ? z : dz[pipeline-1] / dd[pipeline-1] : 0;
	      qc = count > z_width-3 ? qr : 0;
	      sr = count > z_width-3 ? dz[pipeline-1] - (dd[pipeline-1] * qc) : 0;
	      sc = count > z_width-3 ? sr : 0;

	      count <= count > z_width ? count : count + 1;

//	      if (!ovf && !div0 && count > 7)	
	      if(!ovf && !div0)
	      begin
		if ( (qc !== q) || (sc !== s) )
		begin
		  $display("Result error (z/d=%d/%d). Received (q,s) = (%d,%d), expected (%d,%d) div0=%d ovf=%d at time=%0t",
			dz[pipeline-1], dd[pipeline-1], q, s, qc, sc, div0, ovf, $time);
		  err_cnt = err_cnt +1;
		end
		else if(show_res) 
		begin
		  $display("Result      %d/%d = (%d,%d)	div0=%d at time=%0t", dz[pipeline-1], dd[pipeline-1], qc, sc, div0,$time);
		end
	      end

	      if (show_div0)
		if (div0)
		  $display("Division by zero (z/d=%d/%d)", dz[pipeline-1], dd[pipeline-1]);

	      if (show_ovf)
	      begin
		if(test_ovf)
		begin
//		  if (ovf && qc == 128 && (q*dd[pipeline-1]+s)==dz[pipeline-1])
		  if (ovf && (q*dd[pipeline-1]+s)==dz[pipeline-1]) 
	          begin
		    $display("%t: OVERFLOW -> %d/%d = (%d,%d), recieved (%d,%d)",$time,dz[pipeline-1],dd[pipeline-1],qc,sc,q,s);
		    $stop;
		  end
		end
	    	else
		  $display("Overflow (z/d=%d/%d)", dz[pipeline-1], dd[pipeline-1]);
              end

	      @(posedge clk);
	    end

	    // wait a while
	    repeat(20) @(posedge clk);

	    $display("*");
	    $display("* Testbench ended. Total errors = %d", err_cnt);
	    $display("*");
 	    $stop;
	end

endmodule