uu_noreset.v

Verilog jpec coder encoder source code

/* 13 - cycle From input to Output */

`timescale 1ns / 10ps

module div_uu(clk, ena, z, d, q, s, div0, ovf);

	//
	// parameters
	//
//	parameter z_width = 12;
//	parameter d_width = z_width / 2;
//	parameter z_width = 14;
//	parameter d_width = z_width / 2;
	parameter z_width = 24;
  	parameter d_width = z_width / 2;	


	//
	// inputs & outputs
	//
	input clk;	// system clock
	input ena; 	// clock enable

	input  [z_width -1:0] z; //dividend
	input  [d_width -1:0] d; //divisor
	output [d_width -1:0] q; //quotient
	reg    [d_width -1:0] q;
	output [d_width -1:0] s; // remainder
	reg    [d_width -1:0] s;
/*
  //TEST: Trying to fix overflow
  output [d_width-1:0] q; //quotient
  reg [d_width:0] q_ext; //extended quotient
  output [d_width-1:0] s; //remainder
  reg [d_width:0] s_ext; //extended remainder
*/
	output div0;	//Divide By Zero Error
	reg    div0;
	output ovf;	//Overflow Error
	reg    ovf;

	//
	// variables
	//
//	reg [d_width-1:0] q_pipe  [d_width-1:0];

        reg [d_width:0] q_pipe  [d_width-1:0];
	reg [z_width:0] s_pipe  [d_width  :0];
	reg [z_width:0] d_pipe  [d_width  :0];

	reg [d_width:0] div0_pipe, ovf_pipe;

	wire [z_width:0] spipe0  = s_pipe[0];
	wire [z_width:0] spipe1  = s_pipe[1];
	wire [z_width:0] spipe2  = s_pipe[2];
	wire [z_width:0] spipe3  = s_pipe[3];
	wire [z_width:0] spipe4  = s_pipe[4];
	wire [z_width:0] spipe5  = s_pipe[5];
	wire [z_width:0] spipe6  = s_pipe[6];
	wire [z_width:0] spipe7  = s_pipe[7];
	wire [z_width:0] spipe8  = s_pipe[8];
	wire [z_width:0] spipe9  = s_pipe[9];
	wire [z_width:0] spipe10 = s_pipe[10];
	wire [z_width:0] spipe11 = s_pipe[11];
	wire [z_width:0] spipe12 = s_pipe[12];
	
//	wire [z_width:0] qpipe7 = q_pipe[7];

	//Internal Variables
	integer n0, n1;
	  
	// generate divisor (d) pipe
	always @(d)
	  d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };

	always @(posedge clk)
  	  if(ena)
	  begin
		  d_pipe[1] 	<= #1 d_pipe[0];
		  d_pipe[2]		<= #1 d_pipe[1];
		  d_pipe[3]		<= #1 d_pipe[2];
		  d_pipe[4]		<= #1 d_pipe[3];
		  d_pipe[5]		<= #1 d_pipe[4];
		  d_pipe[6]		<= #1 d_pipe[5];
		  d_pipe[7]		<= #1 d_pipe[6];
		  d_pipe[8]		<= #1 d_pipe[7];
		  d_pipe[9]		<= #1 d_pipe[8];
		  d_pipe[10]	<= #1 d_pipe[9];
		  d_pipe[11]	<= #1 d_pipe[10];
		  d_pipe[12]	<= #1 d_pipe[11];
	  end
	    //for(n0=1; n0<=d_width; n0 = n0+1) //1->12
	      //d_pipe[n0] <= #1 d_pipe[n0-1];

	// generate internal remainder pipe
	always @(z)
	  s_pipe[0] <= z;

	always @(posedge clk)
	  if(ena)
          begin	
	    s_pipe[1]  <= #1 spipe0[z_width]  ? (spipe0  << 1) + d_pipe[0]  : (spipe0  << 1) - d_pipe[0];
	    s_pipe[2]  <= #1 spipe1[z_width]  ? (spipe1  << 1) + d_pipe[1]  : (spipe1  << 1) - d_pipe[1];
	    s_pipe[3]  <= #1 spipe2[z_width]  ? (spipe2  << 1) + d_pipe[2]  : (spipe2  << 1) - d_pipe[2];
	    s_pipe[4]  <= #1 spipe3[z_width]  ? (spipe3  << 1) + d_pipe[3]  : (spipe3  << 1) - d_pipe[3];
            s_pipe[5]  <= #1 spipe4[z_width]  ? (spipe4  << 1) + d_pipe[4]  : (spipe4  << 1) - d_pipe[4];
	    s_pipe[6]  <= #1 spipe5[z_width]  ? (spipe5  << 1) + d_pipe[5]  : (spipe5  << 1) - d_pipe[5];
	    s_pipe[7]  <= #1 spipe6[z_width]  ? (spipe6  << 1) + d_pipe[6]  : (spipe6  << 1) - d_pipe[6];		
	    s_pipe[8]  <= #1 spipe7[z_width]  ? (spipe7  << 1) + d_pipe[7]  : (spipe7  << 1) - d_pipe[7];
	    s_pipe[9]  <= #1 spipe8[z_width]  ? (spipe8  << 1) + d_pipe[8]  : (spipe8  << 1) - d_pipe[8];
	    s_pipe[10] <= #1 spipe9[z_width]  ? (spipe9  << 1) + d_pipe[9]  : (spipe9  << 1) - d_pipe[9];
	    s_pipe[11] <= #1 spipe10[z_width] ? (spipe10 << 1) + d_pipe[10] : (spipe10 << 1) - d_pipe[10]; 
	    s_pipe[12] <= #1 spipe11[z_width] ? (spipe11 << 1) + d_pipe[11] : (spipe11 << 1) - d_pipe[11]; 
	  end
	
	// generate quotient pipe
	always @(posedge clk)
		q_pipe[0] <= 0;
	  //q_pipe[0] <= #1 0;

	always @(posedge clk)
	  if(ena)
	  begin
	    q_pipe[1]  <= #1 {(q_pipe[0]), ~spipe1[z_width]};
	    q_pipe[2]  <= #1 {(q_pipe[1]), ~spipe2[z_width]};
	    q_pipe[3]  <= #1 {(q_pipe[2]), ~spipe3[z_width]};
	    q_pipe[4]  <= #1 {(q_pipe[3]), ~spipe4[z_width]};
	    q_pipe[5]  <= #1 {(q_pipe[4]), ~spipe5[z_width]};
	    q_pipe[6]  <= #1 {(q_pipe[5]), ~spipe6[z_width]};
	    q_pipe[7]  <= #1 {(q_pipe[6]), ~spipe7[z_width]};
	    q_pipe[8]  <= #1 {(q_pipe[7]), ~spipe8[z_width]};
	    q_pipe[9]  <= #1 {(q_pipe[8]), ~spipe9[z_width]};
	    q_pipe[10] <= #1 {(q_pipe[9]), ~spipe10[z_width]};
	    q_pipe[11] <= #1 {(q_pipe[10]),~spipe11[z_width]};
	    /*
	    q_pipe[1] <= #1 {(q_pipe[0] << 1),~spipe1[z_width]};
	    q_pipe[2] <= #1 {(q_pipe[1] << 1),~spipe2[z_width]};
	    q_pipe[3] <= #1 {(q_pipe[2] << 1),~spipe3[z_width]};
	    q_pipe[4] <= #1 {(q_pipe[3] << 1),~spipe4[z_width]};
	    q_pipe[5] <= #1 {(q_pipe[4] << 1),~spipe5[z_width]};	
	    */
	  end
		
	// flags (divide_by_zero, overflow)
	always @(z or d)
	begin
	  ovf_pipe[0]  <= !(z[z_width-1:d_width] < d);
	  div0_pipe[0] <= ~|d;
	end

	always @(posedge clk)
	if(ena)
	begin
		ovf_pipe[1]		<= ovf_pipe[0];
		ovf_pipe[2]		<= ovf_pipe[1];
		ovf_pipe[3]		<= ovf_pipe[2];
		ovf_pipe[4]		<= ovf_pipe[3];
		ovf_pipe[5]		<= ovf_pipe[4];
		ovf_pipe[6]		<= ovf_pipe[5];
		ovf_pipe[7]		<= ovf_pipe[6];
		ovf_pipe[8]		<= ovf_pipe[7];
		ovf_pipe[9]		<= ovf_pipe[8];
		ovf_pipe[10]	<= ovf_pipe[9];
		ovf_pipe[11]	<= ovf_pipe[10];
		ovf_pipe[12]	<= ovf_pipe[11];
		div0_pipe[1]	<= div0_pipe[0];
		div0_pipe[2]	<= div0_pipe[1];
		div0_pipe[3]	<= div0_pipe[2];
		div0_pipe[4]	<= div0_pipe[3];
		div0_pipe[5]	<= div0_pipe[4];
		div0_pipe[6]	<= div0_pipe[5];
		div0_pipe[7]	<= div0_pipe[6];
		div0_pipe[8]	<= div0_pipe[7];
		div0_pipe[9]	<= div0_pipe[8];
		div0_pipe[10]	<= div0_pipe[9];
		div0_pipe[11]	<= div0_pipe[10];
		div0_pipe[12]	<= div0_pipe[11];
		/*
		ovf_pipe[1]		<= #1 ovf_pipe[0];
		ovf_pipe[2]		<= #1 ovf_pipe[1];
		ovf_pipe[3]		<= #1 ovf_pipe[2];
		ovf_pipe[4]		<= #1 ovf_pipe[3];
		ovf_pipe[5]		<= #1 ovf_pipe[4];
		ovf_pipe[6]		<= #1 ovf_pipe[5];
		ovf_pipe[7]		<= #1 ovf_pipe[6];
		ovf_pipe[8]		<= #1 ovf_pipe[7];
		ovf_pipe[9]		<= #1 ovf_pipe[8];
		ovf_pipe[10]	<= #1 ovf_pipe[9];
		ovf_pipe[11]	<= #1 ovf_pipe[10];
		ovf_pipe[12]	<= #1 ovf_pipe[11];
		div0_pipe[1]	<= #1 div0_pipe[0];
		div0_pipe[2]	<= #1 div0_pipe[1];
		div0_pipe[3]	<= #1 div0_pipe[2];
		div0_pipe[4]	<= #1 div0_pipe[3];
		div0_pipe[5]	<= #1 div0_pipe[4];
		div0_pipe[6]	<= #1 div0_pipe[5];
		div0_pipe[7]	<= #1 div0_pipe[6];
		div0_pipe[8]	<= #1 div0_pipe[7];
		div0_pipe[9]	<= #1 div0_pipe[8];
		div0_pipe[10]	<= #1 div0_pipe[9];
		div0_pipe[11]	<= #1 div0_pipe[10];
		div0_pipe[12]	<= #1 div0_pipe[11];
		*/
	end
	  /*for(n1=1; n1 <= d_width; n1=n1+1) //1->12
	    begin
	      ovf_pipe[n1] <= #1 ovf_pipe[n1-1];
	      div0_pipe[n1] <= #1 div0_pipe[n1-1];
	    end
*/
	// assign outputs
	always @(posedge clk)
          if(ena)
	  begin
/*	    if(qpipe7 == 8'h80)
	      ovf <= #1 1'b0;
            else
*/
	     // ovf <= #1 ovf_pipe[d_width];
		 ovf <= ovf_pipe[d_width];
	  end

	always @(posedge clk)
	  if(ena)
	    div0 <= /*#1*/ div0_pipe[d_width];

	always @(posedge clk)
	  if(ena)
//	    q <= #1 {(q_pipe[d_width-1] << 1), ~spipe6[z_width]};
	    q <= /*#1*/ {q_pipe[d_width-1],~spipe12[z_width]};

	always @(posedge clk)
	  if(ena)
	    s <= /*#1*/ (spipe12[z_width] ? spipe12 + d_pipe[12] : spipe12) >> d_width;
endmodule