gencontrol.vhd

高速任意波形产生器控制模块 控制NCO,FIFO

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity gencontrol is
port(clk_250,ctrl_en,locked_in,valid_in:in std_logic;
     ncoen,ncoreset_n,ffen:out std_logic);
end;

architecture one of gencontrol is
  type states is(st0,st1,st2,st3,st4);
  signal currentstate,nextstate:states;

begin

switchtonextstate:process(clk_250)
begin
  if clk_250'event and clk_250='1' then
    currentstate<=nextstate;
  end if;
end process switchtonextstate;

changestatemode:process(currentstate)
begin
  case currentstate is
    when st0=>ncoen<='0';
              ncoreset_n<='0';
              ffen<='0';
              if ctrl_en='1' then
                nextstate<=st1;
              else
                nextstate<=st0;
              end if;
    when st1=>ncoen<='0';
              ncoreset_n<='1';
              ffen<='0';
              if ctrl_en='1' then
                if locked_in='1' then
                  nextstate<=st2;
                else
                  nextstate<=st1;
                end if;
              else
                nextstate<=st0;
              end if;
    when st2=>ncoen<='1';
              ncoreset_n<='1';
              ffen<='0';
              if ctrl_en='1' then
                if valid_in='1' then
                  nextstate<=st3;
                else
                  nextstate<=st2;
                end if;
              else
                nextstate<=st0;
              end if;
    when st3=>ncoen<='1';
              ncoreset_n<='1';
              ffen<='1';
              if ctrl_en='1' then
                if valid_in='0' then
                  nextstate<=st4;
                else
                  nextstate<=st3;
                end if;
              else
                nextstate<=st0;
              end if;
    when st4=>ncoen<='0';
              ncoreset_n<='1';
              ffen<='0';
              if ctrl_en='0' then
                nextstate<=st0;
              else
                nextstate<=st4;
              end if;
    when others=>nextstate<=st0;
  end case;
end process changestatemode;

end;