📄 等精度数字频率计的设计（汇编语言和vhdl语言）.txt
字号:
JC DIVM2E
DIVM2S: INC ADA
MOV R2,AD1
MOV R0,AD3
MOV R1,#ADB
LCALL SUBMBB
DIVM2E: DJNZ R3,DIVM2D
RET
DIVM20: SETB 0F0H
RET
DB 02H,12H
SHIL1: MOV R2,AD0
MOV R0,#ADA
SHIL1B: CLR C
SHILL: MOV A,@R0
RLC A
MOV @R0,A
DEC R0
DJNZ R2,SHILL
RET
COMP2: MOV R1,#ADA ; TAKING CPL BYTE NUM. N IS IN 30H
MOV R2,AD0
COMP2B: SETB C
COMP2L: MOV A,@R1
CPL A
ADDC A,#00H
MOV @R1,A
DEC R1
DJNZ R2,COMP2L
RET
ADDMB: MOV R2,AD0 ; NO SIGN N BYTES ADDS N BYTES
MOV R0,#ADA ; (......4FH)+(......5FH)=(......4FH)
MOV R1,#ADB
ADDMBB: CLR C
ADDL: MOV A,@R0
ADDC A,@R1
MOV @R0,A
DEC R0
DEC R1
DJNZ R2,ADDL
RET
SUBMB: MOV R2,AD0 ; NO SIGN N BYTES MINUSE N BYTES
MOV R0,#ADA ; (......4FH)-(......5FH)=(......4FH)
MOV R1,#ADB
SUBMBB: CLR C
SUBMB1: MOV A,@R0
SUBB A,@R1
MOV @R0,A
DEC R0
DEC R1
DJNZ R2,SUBMB1
RET
AD0 EQU 30H
AD1 EQU 31H
AD2 EQU 32H
AD3 EQU 33H
AD4 EQU 34H
AD5 EQU 35H
AD6 EQU 36H
ADA EQU 4FH
ADB EQU 5FH
ADC EQU 4DH
ADDV EQU 5DH
MULNM: NOP ; N BYTES X M BYTES = N+M BYTES HERE N=3;M=3
MOV 30H,#06H ; (4D,4E,4FH)*(5D,5E,5FH)=(5A--5FH)
MOV 31H,#06H
MULTT: MOV A,AD0
MOV R3,AD1
MOV R2,A
ADD A,R3
INC A
MOV AD2,A
MOV A,#ADB
CLR C
SUBB A,R3
MOV AD6,A
MOV R1,A
SUBB A,R2
MOV AD5,A
INC R2
MULNMZ: MOV @R1,#00H
DEC R1
DJNZ R2,MULNMZ
MULNMB: MOV R2,AD0
MOV R1,AD6
MOV R0,#ADA
CLR 00H
MULNML: MOV A,ADB
JZ MULNMD
MOV B,@R0
MUL AB
ADD A,@R1
MOV @R1,A
JNB 00H,MULNM1
INC B
MULNM1: MOV A,B
DEC R1
ADDC A,@R1
MOV @R1,A
MOV 00H,C
DEC R0
DJNZ R2,MULNML
MULNMD: MOV R0,AD5
CLR A
MOV R2,AD2
MULNMS: XCH A,@R0
INC R0
DJNZ R2,MULNMS
DJNZ R3,MULNMB
RET
; LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL
KKEYII:LCALL KKS1
JNZ KLK1
KNN1: LCALL DELAY
LCALL DELAY
SETB 28H.3
RET
KKEYI:LCALL KKS1
JNZ KLK1
KN1:LCALL DELAY
LCALL DELAY
LJMP KKEYI
KLK1:LCALL DELAY
LCALL DELAY
LCALL KKS1
JNZ KLK2
LCALL DELAY
LJMP KKEYI
KLK2:NOP
JB P1.0,NOK1
MOV A,#00H
LJMP GOHM
NOK1:NOP
JB P1.1,NOK2
MOV A,#01H
LJMP GOHM
NOK2:NOP
JB P1.2,NOK3
MOV A,#02H
LJMP GOHM
NOK3:NOP
JB P1.3,NOK4
MOV A,#03H
LJMP GOHM
NOK4:NOP
JB P1.4,NOK5
MOV A,#04H
LJMP GOHM
NOK5:NOP
JB P1.5,NOK6
MOV A,#05H
LJMP GOHM
NOK6:NOP
JB P1.6,NOK7
MOV A,#06H
LJMP GOHM
NOK7:NOP
JB P1.7,KLK1
MOV A,#07H
GOHM:PUSH ACC
KLK3:LCALL DELAY
LCALL KKS1
JNZ KLK3
LCALL DELAY
LCALL KKS1
JNZ KLK3
POP ACC
CLR 28H.3
RET
KKS1:MOV P1,#0FFH
NOP
MOV A,P1
CPL A
RET
DELAY:MOV R1,#09H
WWW:MOV R0,#0FFH
NMN:DJNZ R0,NMN
DJNZ R1,WWW
RET
; TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT
NL0: MOV R0,#10H
MOV R1,#0EH
CLRRT: MOV @R0,#12H
INC R0
DJNZ R1,CLRRT
RET
END
LIBRARY IEEE; -- 2004；GWDVPB 选择模式5
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY etester IS
PORT (BCLK : IN STD_LOGIC; --标准频率时钟信号CLOCK2：P124
TCLK : IN STD_LOGIC; --PIO16 待测频率时钟信号：P39
CLR : IN STD_LOGIC; --PIO0 清零和初始化信号：P1
CLRO : BUFFER STD_LOGIC;
CL : IN STD_LOGIC; --PIO1 当SPUL为高电平时，CL为预置门控信号，用于测频计数时间控制
--当SPUL为低电平时，CL为测脉宽控制信号，CL高电平时测高电平脉宽
--而当CL为低电平时，测低电平脉宽。：P2
CLO : BUFFER STD_LOGIC;
SPUL : IN STD_LOGIC; --PIO2 测频或测脉宽控制：P3
SPULO : BUFFER STD_LOGIC;
START : OUT STD_LOGIC; --PIO7：P10
EEND : OUT STD_LOGIC; --PIO3 由低电平变到高电平时指示脉宽计数结束：P4?
START1 : OUT STD_LOGIC; --PIO7：P10
EEND1 : OUT STD_LOGIC; --PIO3 由低电平变到高电平时指示脉宽计数结束：P4，
SEL : IN STD_LOGIC_VECTOR(2 DOWNTO 0); --PIO6/PIO5/PIO4：P7、P6、P5
--两个32位计数器计数值分8位读出多路选择控制
SELO : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --PIO6/PIO5/PIO4：P7、P6、P5
SELE : IN STD_LOGIC_VECTOR(1 DOWNTO 0); --PIO6/PIO5/PIO4：P7、P6、P5
DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --PIO8/9/10/11/12/13/14/15 8位数据读出
DATA1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --PIO8/9/10/11/12/13/14/15 8位数据读出
CLK:IN STD_LOGIC;
SEC1:OUT STD_LOGIC;
SEC2:OUT STD_LOGIC); --P11、P32、P33、P34、P35、P36、P37、P38
END etester;
ARCHITECTURE behav OF etester IS
COMPONENT sec is
port(CLK:in std_logic;
SEC1:out std_logic;
SEC2:OUT STD_LOGIC);
end COMPONENT sec;
SIGNAL BZQ : STD_LOGIC_VECTOR(31 DOWNTO 0); --标准计数器
SIGNAL TSQ : STD_LOGIC_VECTOR(31 DOWNTO 0); --测频计数器
SIGNAL ENA : STD_LOGIC; -- 计数使能
SIGNAL MA : STD_LOGIC;
SIGNAL CLK1 : STD_LOGIC;
SIGNAL CLK2 : STD_LOGIC;
SIGNAL CLK3 : STD_LOGIC;
SIGNAL Q1 : STD_LOGIC;
SIGNAL Q2 : STD_LOGIC;
SIGNAL Q3 : STD_LOGIC;
SIGNAL BENA : STD_LOGIC;
SIGNAL PUL : STD_LOGIC; --脉宽计数使能
SIGNAL SS : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
U0:SEC PORT MAP(CLK,SEC1,SEC2);
START <= ENA ;
START1 <= ENA ;
DATA <= BZQ(7 DOWNTO 0) WHEN SEL = "000" ELSE -- 标准频率计数低8位输出
BZQ(15 DOWNTO 8) WHEN SEL = "001" ELSE
BZQ(23 DOWNTO 16) WHEN SEL = "010" ELSE
BZQ(31 DOWNTO 24) WHEN SEL = "011" ELSE -- 标准频率计数最高8位输出
TSQ(7 DOWNTO 0) WHEN SEL = "100" ELSE --待测频率计数值最低8位输出
TSQ(15 DOWNTO 8) WHEN SEL = "101" ELSE
TSQ(23 DOWNTO 16) WHEN SEL = "110" ELSE
TSQ(31 DOWNTO 24) WHEN SEL = "111" ELSE --待测频率计数值最高8位输出
TSQ(31 DOWNTO 24) ;
DATA1 <= BZQ(15 DOWNTO 0) WHEN SELE = "00" ELSE
BZQ(31 DOWNTO 16) WHEN SELE = "01" ELSE
TSQ(15 DOWNTO 0) WHEN SELE = "10" ELSE
TSQ(31 DOWNTO 16) WHEN SELE = "11" ELSE
TSQ(31 DOWNTO 16);
-- HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
BZH : PROCESS(BCLK, CLR) --标准频率测试计数器，标准计数器
BEGIN
IF CLR = '1' THEN BZQ <= ( OTHERS=>'0' ) ;
ELSIF BCLK'EVENT AND BCLK = '1' THEN
IF BENA = '1' THEN BZQ <= BZQ + 1;
END IF;
END IF;
END PROCESS;
-- gggggggggggggggggggggggggggggggggggggggggggggggggggg
TF : PROCESS(TCLK, CLR, ENA) --待测频率计数器，测频计数器
BEGIN
IF CLR = '1' THEN TSQ <= ( OTHERS=>'0' );
ELSIF TCLK'EVENT AND TCLK = '1' THEN
IF ENA = '1' THEN TSQ <= TSQ + 1;
END IF;
END IF;
END PROCESS;
--FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
PROCESS(TCLK,CLR) --计数控制使能触发器，CL为预置门控信号，同时兼作正负脉宽测试控制信号
BEGIN
IF CLR = '1' THEN ENA <= '0' ;
ELSIF TCLK'EVENT AND TCLK = '1' THEN
ENA <= CL ;
END IF;
END PROCESS;
--OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO
MA <= (TCLK AND CL) OR NOT(TCLK OR CL) ; --测脉宽逻辑
CLK1 <= NOT MA ;
CLK2 <= MA AND Q1 ;
CLK3 <= NOT CLK2 ;
SS <= Q2 & Q3 ;
-- HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
DD1: PROCESS(CLK1,CLR)
BEGIN
IF CLR = '1' THEN Q1 <= '0' ;
ELSIF CLK1'EVENT AND CLK1 = '1' THEN Q1 <= '1' ;
END IF;
END PROCESS;
DD2: PROCESS(CLK2,CLR)
BEGIN
IF CLR = '1' THEN Q2 <= '0' ;
ELSIF CLK2'EVENT AND CLK2 = '1' THEN Q2 <= '1' ;
END IF;
END PROCESS;
DD3: PROCESS(CLK3,CLR)
BEGIN
IF CLR = '1' THEN Q3 <= '0' ;
ELSIF CLK3'EVENT AND CLK3 = '1' THEN Q3 <= '1' ;
END IF;
END PROCESS;
-- HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
GT :
PUL <= '1' WHEN SS = "10" ELSE --当SS=“10”时，PUL高电平，允许标准计数器计数，
'0' ; --禁止计数
EEND <= '1' WHEN SS = "11" ELSE --EEND为低电平时，表示正在计数，由低电平变到高电平
'0' ; --时，表示计数结束，可以从标准计数器中读数据了
EEND1 <= '1' WHEN SS = "11" ELSE --EEND为低电平时，表示正在计数，由低电平变到高电平
'0' ; --时，表示计数结束，可以从标准计数器中读数据了
--UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
BENA <= ENA WHEN SPUL = '1' ELSE --标准计数器时钟使能控制信号，当SPUL为1时，测频率
PUL WHEN SPUL = '0' ELSE --当SPUL为0时，测脉宽和占空比
PUL ;
PROCESS(CLR,CL,SPUL,SEL)
BEGIN
IF CLR'EVENT AND CLR = '1' THEN CLRO <= NOT CLRO;
END IF;
IF CL'EVENT AND CL = '1' THEN CLO <= NOT CLO;
END IF;
IF SPUL'EVENT AND SPUL = '1' THEN SPULO <= NOT SPULO;
END IF;
SELO <= SEL;
END PROCESS;
--UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
END behav;
-SEC.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY SEC IS
PORT(CLK:IN STD_LOGIC;
SEC1:OUT STD_LOGIC;
SEC2:OUT STD_LOGIC);
END ENTITY SEC;
ARCHITECTURE ART OF SEC IS
SIGNAL CNT4:INTEGER RANGE 0 TO 3;
SIGNAL CLK1:STD_LOGIC;
BEGIN
PROCESS(CLK,CLK1)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
IF CNT4=3 THEN
CNT4<=0;
CLK1<=NOT CLK1;
ELSE
CNT4<=CNT4+1;
END IF;
ELSE
CLK1<=CLK1;
END IF;
SEC1<=CLK1;
SEC2<=CLK1;
END PROCESS;
END ARCHITECTURE ART;
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