📄 defeqns.htm
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FTCPE_rma/ram_12_4: FTCPE port map (rma/ram_12_4,rma/ram_12_4_T,clk,'0','0');
<br/> rma/ram_12_4_T <= ((rma/ram_12_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_12_5: FTCPE port map (rma/ram_12_5,rma/ram_12_5_T,clk,'0','0');
<br/> rma/ram_12_5_T <= ((rma/ram_12_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_12_6: FTCPE port map (rma/ram_12_6,rma/ram_12_6_T,clk,'0','0');
<br/> rma/ram_12_6_T <= ((rma/ram_12_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_12_7: FTCPE port map (rma/ram_12_7,rma/ram_12_7_T,clk,'0','0');
<br/> rma/ram_12_7_T <= ((rma/ram_12_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_0: FTCPE port map (rma/ram_13_0,rma/ram_13_0_T,clk,'0','0');
<br/> rma/ram_13_0_T <= ((rma/ram_13_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_1: FTCPE port map (rma/ram_13_1,rma/ram_13_1_T,clk,'0','0');
<br/> rma/ram_13_1_T <= ((rma/ram_13_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_2: FTCPE port map (rma/ram_13_2,rma/ram_13_2_T,clk,'0','0');
<br/> rma/ram_13_2_T <= ((rma/ram_13_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_3: FTCPE port map (rma/ram_13_3,rma/ram_13_3_T,clk,'0','0');
<br/> rma/ram_13_3_T <= ((rma/ram_13_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_4: FTCPE port map (rma/ram_13_4,rma/ram_13_4_T,clk,'0','0');
<br/> rma/ram_13_4_T <= ((rma/ram_13_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_5: FTCPE port map (rma/ram_13_5,rma/ram_13_5_T,clk,'0','0');
<br/> rma/ram_13_5_T <= ((rma/ram_13_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_6: FTCPE port map (rma/ram_13_6,rma/ram_13_6_T,clk,'0','0');
<br/> rma/ram_13_6_T <= ((rma/ram_13_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_13_7: FTCPE port map (rma/ram_13_7,rma/ram_13_7_T,clk,'0','0');
<br/> rma/ram_13_7_T <= ((rma/ram_13_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_13_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_0: FTCPE port map (rma/ram_14_0,rma/ram_14_0_T,clk,'0','0');
<br/> rma/ram_14_0_T <= ((rma/ram_14_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_1: FTCPE port map (rma/ram_14_1,rma/ram_14_1_T,clk,'0','0');
<br/> rma/ram_14_1_T <= ((rma/ram_14_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_2: FTCPE port map (rma/ram_14_2,rma/ram_14_2_T,clk,'0','0');
<br/> rma/ram_14_2_T <= ((rma/ram_14_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_3: FTCPE port map (rma/ram_14_3,rma/ram_14_3_T,clk,'0','0');
<br/> rma/ram_14_3_T <= ((rma/ram_14_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_4: FTCPE port map (rma/ram_14_4,rma/ram_14_4_T,clk,'0','0');
<br/> rma/ram_14_4_T <= ((rma/ram_14_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_5: FTCPE port map (rma/ram_14_5,rma/ram_14_5_T,clk,'0','0');
<br/> rma/ram_14_5_T <= ((rma/ram_14_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_6: FTCPE port map (rma/ram_14_6,rma/ram_14_6_T,clk,'0','0');
<br/> rma/ram_14_6_T <= ((rma/ram_14_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_14_7: FTCPE port map (rma/ram_14_7,rma/ram_14_7_T,clk,'0','0');
<br/> rma/ram_14_7_T <= ((rma/ram_14_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_14_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_15_0: FTCPE port map (rma/ram_15_0,rma/ram_15_0_T,clk,'0','0');
<br/> rma/ram_15_0_T <= ((rma/ram_15_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_15_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_15_1: FTCPE port map (rma/ram_15_1,rma/ram_15_1_T,clk,'0','0');
<br/> rma/ram_15_1_T <= ((rma/ram_15_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_15_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_15_2: FTCPE port map (rma/ram_15_2,rma/ram_15_2_T,clk,'0','0');
<br/> rma/ram_15_2_T <= ((rma/ram_15_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_15_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_15_3: FTCPE port map (rma/ram_15_3,rma/ram_15_3_T,clk,'0','0');
<br/> rma/ram_15_3_T <= ((rma/ram_15_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_15_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_15_4: FTCPE port map (rma/ram_15_4,rma/ram_15_4_T,clk,'0','0');
<br/> rma/ram_15_4_T <= ((rma/ram_15_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_15_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_15_5: FTCPE port map (rma/ram_15_5,rma/ram_15_5_T,clk,'0','0');
<br/> rma/ram_15_5_T <= ((rma/ram_15_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_15_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_15_6: FTCPE port map (rma/ram_15_6,rma/ram_15_6_T,clk,'0','0');
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