📄 defeqns.htm
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FTCPE_rma/ram_0_2: FTCPE port map (rma/ram_0_2,rma/ram_0_2_T,clk,'0','0');
<br/> rma/ram_0_2_T <= ((rma/ram_0_2 AND wr_en AND NOT di(2) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_2 AND wr_en AND di(2) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_0_3: FTCPE port map (rma/ram_0_3,rma/ram_0_3_T,clk,'0','0');
<br/> rma/ram_0_3_T <= ((rma/ram_0_3 AND wr_en AND NOT di(3) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_3 AND wr_en AND di(3) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_0_4: FTCPE port map (rma/ram_0_4,rma/ram_0_4_T,clk,'0','0');
<br/> rma/ram_0_4_T <= ((rma/ram_0_4 AND wr_en AND NOT di(4) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_4 AND wr_en AND di(4) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_0_5: FTCPE port map (rma/ram_0_5,rma/ram_0_5_T,clk,'0','0');
<br/> rma/ram_0_5_T <= ((rma/ram_0_5 AND wr_en AND NOT di(5) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_5 AND wr_en AND di(5) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_0_6: FTCPE port map (rma/ram_0_6,rma/ram_0_6_T,clk,'0','0');
<br/> rma/ram_0_6_T <= ((rma/ram_0_6 AND wr_en AND NOT di(6) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_6 AND wr_en AND di(6) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_0_7: FTCPE port map (rma/ram_0_7,rma/ram_0_7_T,clk,'0','0');
<br/> rma/ram_0_7_T <= ((rma/ram_0_7 AND wr_en AND NOT di(7) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_7 AND wr_en AND di(7) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_0: FTCPE port map (rma/ram_10_0,rma/ram_10_0_T,clk,'0','0');
<br/> rma/ram_10_0_T <= ((rma/ram_10_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_1: FTCPE port map (rma/ram_10_1,rma/ram_10_1_T,clk,'0','0');
<br/> rma/ram_10_1_T <= ((rma/ram_10_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_2: FTCPE port map (rma/ram_10_2,rma/ram_10_2_T,clk,'0','0');
<br/> rma/ram_10_2_T <= ((rma/ram_10_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_3: FTCPE port map (rma/ram_10_3,rma/ram_10_3_T,clk,'0','0');
<br/> rma/ram_10_3_T <= ((rma/ram_10_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_4: FTCPE port map (rma/ram_10_4,rma/ram_10_4_T,clk,'0','0');
<br/> rma/ram_10_4_T <= ((rma/ram_10_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_5: FTCPE port map (rma/ram_10_5,rma/ram_10_5_T,clk,'0','0');
<br/> rma/ram_10_5_T <= ((rma/ram_10_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_6: FTCPE port map (rma/ram_10_6,rma/ram_10_6_T,clk,'0','0');
<br/> rma/ram_10_6_T <= ((rma/ram_10_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_10_7: FTCPE port map (rma/ram_10_7,rma/ram_10_7_T,clk,'0','0');
<br/> rma/ram_10_7_T <= ((rma/ram_10_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_10_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_0: FTCPE port map (rma/ram_11_0,rma/ram_11_0_T,clk,'0','0');
<br/> rma/ram_11_0_T <= ((rma/ram_11_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_1: FTCPE port map (rma/ram_11_1,rma/ram_11_1_T,clk,'0','0');
<br/> rma/ram_11_1_T <= ((rma/ram_11_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_2: FTCPE port map (rma/ram_11_2,rma/ram_11_2_T,clk,'0','0');
<br/> rma/ram_11_2_T <= ((rma/ram_11_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_3: FTCPE port map (rma/ram_11_3,rma/ram_11_3_T,clk,'0','0');
<br/> rma/ram_11_3_T <= ((rma/ram_11_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_4: FTCPE port map (rma/ram_11_4,rma/ram_11_4_T,clk,'0','0');
<br/> rma/ram_11_4_T <= ((rma/ram_11_4 AND wr_en AND NOT di(4) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_4 AND wr_en AND di(4) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_5: FTCPE port map (rma/ram_11_5,rma/ram_11_5_T,clk,'0','0');
<br/> rma/ram_11_5_T <= ((rma/ram_11_5 AND wr_en AND NOT di(5) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_5 AND wr_en AND di(5) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_6: FTCPE port map (rma/ram_11_6,rma/ram_11_6_T,clk,'0','0');
<br/> rma/ram_11_6_T <= ((rma/ram_11_6 AND wr_en AND NOT di(6) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_6 AND wr_en AND di(6) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_11_7: FTCPE port map (rma/ram_11_7,rma/ram_11_7_T,clk,'0','0');
<br/> rma/ram_11_7_T <= ((rma/ram_11_7 AND wr_en AND NOT di(7) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_11_7 AND wr_en AND di(7) AND ys(3)/ys(3)_D2 AND
<br/> ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_12_0: FTCPE port map (rma/ram_12_0,rma/ram_12_0_T,clk,'0','0');
<br/> rma/ram_12_0_T <= ((rma/ram_12_0 AND wr_en AND NOT di(0) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_0 AND wr_en AND di(0) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_12_1: FTCPE port map (rma/ram_12_1,rma/ram_12_1_T,clk,'0','0');
<br/> rma/ram_12_1_T <= ((rma/ram_12_1 AND wr_en AND NOT di(1) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_1 AND wr_en AND di(1) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_12_2: FTCPE port map (rma/ram_12_2,rma/ram_12_2_T,clk,'0','0');
<br/> rma/ram_12_2_T <= ((rma/ram_12_2 AND wr_en AND NOT di(2) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_2 AND wr_en AND di(2) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_12_3: FTCPE port map (rma/ram_12_3,rma/ram_12_3_T,clk,'0','0');
<br/> rma/ram_12_3_T <= ((rma/ram_12_3 AND wr_en AND NOT di(3) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_12_3 AND wr_en AND di(3) AND ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
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