📄 defeqns.htm
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<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_4 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FDCPE_do5: FDCPE port map (do(5),do_D(5),clk,'0','0',rd_en);
<br/> do_D(5) <= ((rma/ram_15_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_5 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_5 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_5 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_5 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FDCPE_do6: FDCPE port map (do(6),do_D(6),clk,'0','0',rd_en);
<br/> do_D(6) <= ((rma/ram_15_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_6 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_6 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_6 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_6 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FDCPE_do7: FDCPE port map (do(7),do_D(7),clk,'0','0',rd_en);
<br/> do_D(7) <= ((rma/ram_15_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_7 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_7 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_7 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_7 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
** Buried Nodes **
</td></tr><tr><td>
FDCPE_ds0: FDCPE port map (ds(0),qs(2),clk,'0','0');
</td></tr><tr><td>
FDCPE_ds1: FDCPE port map (ds(1),qs(3),clk,'0','0');
</td></tr><tr><td>
FDCPE_ds2: FDCPE port map (ds(2),qs(0),clk,'0','0');
</td></tr><tr><td>
FDCPE_ds3: FDCPE port map (ds(3),qs(1),clk,'0','0');
</td></tr><tr><td>
FTCPE_qs0: FTCPE port map (qs(0),'1',clk,clr,'0',ena);
</td></tr><tr><td>
FTCPE_qs1: FTCPE port map (qs(1),qs(0),clk,clr,'0',ena);
</td></tr><tr><td>
FTCPE_qs2: FTCPE port map (qs(2),qs_T(2),clk,clr,'0',ena);
<br/> qs_T(2) <= (qs(0) AND qs(1));
</td></tr><tr><td>
FTCPE_qs3: FTCPE port map (qs(3),qs_T(3),clk,clr,'0',ena);
<br/> qs_T(3) <= (qs(0) AND qs(1) AND qs(2));
</td></tr><tr><td>
FDCPE_rd_en: FDCPE port map (rd_en,'0','0','0',NOT sel);
</td></tr><tr><td>
FTCPE_rma/ram_0_0: FTCPE port map (rma/ram_0_0,rma/ram_0_0_T,clk,'0','0');
<br/> rma/ram_0_0_T <= ((rma/ram_0_0 AND wr_en AND NOT di(0) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_0 AND wr_en AND di(0) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FTCPE_rma/ram_0_1: FTCPE port map (rma/ram_0_1,rma/ram_0_1_T,clk,'0','0');
<br/> rma/ram_0_1_T <= ((rma/ram_0_1 AND wr_en AND NOT di(1) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (NOT rma/ram_0_1 AND wr_en AND di(1) AND NOT ys(3)/ys(3)_D2 AND
<br/> NOT ys(0)/ys(0)_D2 AND NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
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