📄 defeqns.htm
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<h3 align='center'>Equations</h3>
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********** UnMapped Logic **********
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** Outputs **
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FDCPE_do0: FDCPE port map (do(0),do_D(0),clk,'0','0',rd_en);
<br/> do_D(0) <= ((rma/ram_15_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_0 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_0 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_0 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_0 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
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FDCPE_do1: FDCPE port map (do(1),do_D(1),clk,'0','0',rd_en);
<br/> do_D(1) <= ((rma/ram_15_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_1 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_1 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_1 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_1 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FDCPE_do2: FDCPE port map (do(2),do_D(2),clk,'0','0',rd_en);
<br/> do_D(2) <= ((rma/ram_15_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_2 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_2 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_2 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_2 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FDCPE_do3: FDCPE port map (do(3),do_D(3),clk,'0','0',rd_en);
<br/> do_D(3) <= ((rma/ram_15_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_11_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_2_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_4_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_6_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_13_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_8_3 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_0_3 AND NOT ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_9_3 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_3_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_5_3 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2));
</td></tr><tr><td>
FDCPE_do4: FDCPE port map (do(4),do_D(4),clk,'0','0',rd_en);
<br/> do_D(4) <= ((rma/ram_15_4 AND ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_7_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_14_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_1_4 AND NOT ys(3)/ys(3)_D2 AND ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND NOT ys(1)/ys(1)_D2)
<br/> OR (rma/ram_10_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
<br/> NOT ys(2)/ys(2)_D2 AND ys(1)/ys(1)_D2)
<br/> OR (rma/ram_12_4 AND ys(3)/ys(3)_D2 AND NOT ys(0)/ys(0)_D2 AND
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